VCS gate model with SDF reverse standard simulation, change the mem model, the program card at zero moment, didn't go down, prompt 0 time Too many event happens, may exit the zero delay loop, at present there are three kinds of methods: think of
1. + the debug all, start the DVE single-step debugging
2. + + compile options VCS + number + loopreport
3. + + compile options gateloopwarn

In addition to the three other methods?

Also, this kind of question, general big impact? Mem model are commercial IP, RTL simulation have not seen this problem

CodePudding user response:

Logic circuit has a problem, a combinational logic made into a loop, VCS can not determine the true value