This USES STM32 interrupt priority level, at the time of configuration met preemptive priority level and response priority level of these two concepts, see a lot of information all speak too official, for the beginner rookie with me, are the two priority level specific ideas? What is the difference? Why do you want to set up two priorities?
Accidentally met on the Internet for articles, the understanding to the STM32 interrupt priority level of ripe and easy to understand, immediately understand the general meaning of the two priority levels (about) can only say, here to summarize a forget again in the future, OK to:
Preemptive priority levels: namely the preemptive priority level high can interrupt the preemptive priority level low run when strip running kernel preemptive priority interrupt response of the high level, that is to say, low level first, and so on, to run the first level of high running back level low, known as the interrupt nesting, the interruption of high priority grade can be nested in interrupt priority level is low, if the preemptive priority level is no nested relation at the same time, have to run to the end of the current interrupt response and then to run at the same level of the interrupt response,
If two preemptive priority level the same interrupt response at the same time (the difference between good and the above mentioned a) is already running, this depends on the response to a priority level of high and low (also known as the priority level/deputy priority level), the first run high again run low,
So if the preemptive priority level and response priority level are the same then according to their the interruption to the scale of the ligand order,
Note: response priorities is to run an interrupt program an interrupt, if two interrupt signal came to, and take the same priority, then determine the response priority first run, after running the low priority, and this outage program with preemption priority, among different response priority, don't interrupt the currently running program, also can only wait until after the current interrupt program is run run, namely the two break without any nested relation,
Note:
1) if the specified preemptive priority or response to a priority level is beyond the limit imposed by the selected priority group, will likely get unexpected results (burn chip?? );
2) preemptive priority no nested relationship between the same interrupt source;
3) if a particular interrupt source is specified as a preemptive priority level, and no other interrupt source at the same level of preemptive priority, you can specify any effective response for source of the interrupt priority level,
In short: preemptive priority level & gt; Response priorities & gt; Interrupt the sequence in the table,
Another is the concept of grouping, thick see dizziness fog, scan them,
To classification certainly will end up a register configuration, 32 in this register only four and four (because the interrupt source is not much enough)
It is configured as follows, XXXX, QXXX QQXX, QQQX, QQQQ five ways which is 5 groups, this is the concept of group,
0 group: all four priority is used to specify the response
Group 1: the highest one is used to specify the preemptive priority, and minimum 3 is used to specify the response priorities
2 groups: the highest two is used to specify the preemptive priority, the lowest 2 is used to specify the response priorities
Group 3:3 is used to specify the highest preemptive priority, the lowest one is used to specify the response priorities
Group 4: all four is used to specify the preemptive priority,
Then it dawned on the following turn to pick: look at the
ARM kernel architecture (m3, support 256, containing 16 kernel interrupt and 240 external interruption, and have a level 256 programmable interrupt Settings, in the STM32 MCU of ST company up to 84, including 16 kernel interrupt (this is 16 internal interrupt any semiconductor maker also can't change), and 68 maskable interrupt, a programmable interrupt priority level 16, but only in STM32F103 series 60 maskable interrupt, (series 107, 68),
For the 60 maskable Interrupt, the key to master it an Interrupt Priority register group of IPR, the full name of Interrupt Priority Registers, this group contains 15 32-bit Registers, a occupies the first 8 bit maskable Interrupt, so a register can control four maskable Interrupt, a total of 15 * 4=60, however in this takes 8 bit and only use the high bit 4, the allocation of the high bit 4 is STM32F103 microcontroller Interrupt nested set series, series of STM32F103 Interrupt nesting is divided into five groups, respectively is 0,1,2,3,4 the five groups, here are five group, the corresponding relationship between Interrupt nested
Group
Assign the results
0
0 a preemption priority, four response priorities
1
Take priority 1, 3 response priorities
2
Two preemption priority, two response priorities
3
Take priority three, one response priorities
4
Take priority 4, 0 a response priorities
Take priority and response priority for, just remember two points, first, grab any priority than than all response priority priority, only take the higher priority interrupt nesting function, (that is, the interrupt other executing interruption), the second, the smaller the number the higher priority, preemption priority and response priority are all the same, the first response channel corresponds to suspend the interrupt vector address is low,
In the face of 0 and 1 group under do a analysis,
Corresponding take priority is 0, 0 group four priority response, so without preemption priority response priorities can be set to 0 to 15 level 4 power (2), one of
1 set of corresponding take priority is 1, three priority response and then take precedence only levels can be set to 0 or 1 in any of the a (2, 1 power), response priorities can be set to 0 to 7 grade 3 power (2), one of
On electrical reset, interrupt configuration for the four groups, is preempted and 60 external interrupt priority level 0, no response priorities,
So it can be seen when the judge two interrupt priority take priority of see first, if the same look at the response of high and low priority, if all finally see the same interrupt channel vector address,
Generally in use process, a system using a category can completely meet the need, so in the use of a generally don't in the system, and changes to the group after group, hardcore players can try chip burned (carefully),
External interrupt:
STM32F103 external interrupt EXTI support 19 external interrupt requests/events, each interrupt/events are independent of the trigger and block set,
0 to 15 line: corresponding external I/O port interrupt
Line 16: received PVD output
Line 17: received RCT alarm events
Line 18: received USB wake events
Line line 16 to 18, has not been used for my own main 0 to 15 I/O to the line input interrupt to do a summary, there is a note is the external interrupt 0 to 15 line, including 0 to 4 lines, the five external interrupt has its own separate interrupt response function, line 5 to 9 public an interrupt service function, line 10 to 15 public an interrupt service function,
External interrupt configuration register set EXTICR contains four 32-bit registers, respectively is EXTICR0, EXTICR1, EXTICR2, EXTICR3, but each register in the low 16 bits, every four control an I/O port, a register control four I/O port, EXTICR control 16 I/O port register group, just a number of I/O port GPIO EXTICR0, for example, under the expressed in a form:
The I/O port 3
The I/O port 2
The I/O port 1
The I/O port 0
0000 GPIOA
0000 GPIOA
0000 GPIOA
0000 GPIOA
0001 GPIOB
0001 GPIOB
0001 GPIOB
0001 GPIOB
0010 GPIOC
0010 GPIOC
0010 GPIOC
0010 GPIOC
0011 GPIOD
0011 GPIOD
0011 GPIOD
0011 GPIOD
0100 GPIOE
0100 GPIOE
0100 GPIOE
0100 GPIOE
0101 GPIOF
0101 GPIOF
0101 GPIOF
0101 GPIOF
0110 GPIOG
0110 GPIOG
0110 GPIOG
0110 GPIOG
Such as configuration GPIOA. 0 is EXTICR0 low four configuration into 0000, if the configuration GPIOB. 1 is configuration EXTICR0 4 to 7, 0001,
There is a problem, if you want to configure GPIOA. 0 and GPIOB. 0, would cause conflict, don't know if timesharing configuration solution, I use the way of solid base, do not need to consider these, ha ha, pay attention to when using the firmware library interrupt reset function is written in the book of stm32f10x_it c in this file,
Combined with external interrupt attached below the firmware library version of the program:
Main function:
Void NVIC_Configuration (void)
{
NVIC_InitTypeDef NVIC_InitSructure;
NVIC_PriorityGroupConfig (NVIC_PriorityGroup_2);//set to priority group 2
NVIC_InitSructure. NVIC_IRQChannel=EXTI15_10_IRQn;//define external interrupt line 13 interrupt channel
NVIC_InitSructure. NVIC_IRQChannelPreemptionPriority=0;//take priority 0
NVIC_InitSructure. NVIC_IRQChannelSubPriority=0;//response priority 0
NVIC_InitSructure. NVIC_IRQChannelCmd=ENABLE;//can make specified channel
NVIC_Init (& amp; NVIC_InitSructure);
NVIC_InitSructure. NVIC_IRQChannel=EXTI15_10_IRQn;//define external interrupt line 15 interrupt channel
NVIC_InitSructure. NVIC_IRQChannelPreemptionPriority=1;
NVIC_InitSructure. NVIC_IRQChannelSubPriority=1;
NVIC_InitSructure. NVIC_IRQChannelCmd=ENABLE;//can make specified channel
NVIC_Init (& amp; NVIC_InitSructure);
NVIC_InitSructure. NVIC_IRQChannel=EXTI0_IRQn;//define external interrupt line zero interrupt channel
NVIC_InitSructure. NVIC_IRQChannelPreemptionPriority=1;
NVIC_InitSructure. NVIC_IRQChannelSubPriority=1;
NVIC_InitSructure. NVIC_IRQChannelCmd=ENABLE;//can make specified channel
NVIC_Init (& amp; NVIC_InitSructure);
}
Void EXTI_Configuration (void)
{
EXTI_InitTypeDef EXTI_InitStructure;//initialize the structure
GPIO_EXTILineConfig (GPIO_PortSourceGPIOA GPIO_PinSource13);//which indicate the current pin for external interrupt trigger pin
GPIO_EXTILineConfig (GPIO_PortSourceGPIOA GPIO_PinSource15);
EXTI_ClearITPendingBit (EXTI_Line13);//remove the interrupt flag bit EXTI_Line13 corresponding to the corresponding interrupt line 13
EXTI_ClearITPendingBit (EXTI_Line15);
EXTI_InitStructure. EXTI_Mode=EXTI_Mode_Interrupt;//select interrupt mode request
EXTI_InitStructure. EXTI_Trigger=EXTI_Trigger_Falling;//drop along the trigger
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