Go to: http://www.eepw.com.cn/article/184677.htm
The FPGA don't take such a play! To prohibit the simulation using the Quartus II bring yourself, don't draw waveform, it was useless to you as the master (can't master, Quartus II can only make a primary simulation)! If you aspire to in the FPGA industry, the key of Testbench would then write to you, and write the RTL code and don't go to the company, to chairman MAO guarantee, the company must be for you to write a Testbench, then hurriedly threw you how far the FPGA development board how far (don't lost, still need to use), the FPGA is not a single chip microcomputer, learn the FPGA is less need to develop, for example, study the FPGA is the long march of twenty-five thousand li, then using the development board even accounts for less than three miles, far less than that for the FPGA, the simulation is the core, so go ahead and verify the account for 70% of the whole design work, simulation before and after simulation and functional simulation, timing simulation and behavioral level simulation, the RTL simulation, after comprehensive simulation, gate level simulation, the simulation after layout... Well, don't be dizzy, this only speak Testbench, Modelsim simulation we discuss again next,
One of the most basic Testbench contains three parts, the signal definition, module interface and function code, borrow privileged students summary writing Testbench three basic steps:
1, to be instantiated at the top of test design interface;
2, to be test design input interface to add incentives;
3, whether is the output of the test design corresponding meet the design requirements,
Gradually write Testbench these three points:
First "to be the top of the test design interface for example", this step is relatively simple, is instantiated, but also enough to drink a pot of much port, and wire, reg, sometimes wrong, don't be sad, you can actually have a lazy, automatically generated by the Quartus II a Testbench template, select Processing - & gt; Start - & gt; Start the Test Bench Template Writer, wait for after the completion of the open just generate Testbench, default is stored in the simulation \ Modelsim folder. Vt format file, this step is not much talked about, lazy is good,
Second "to be test design input interface to add incentives", is certain to be referred to general sequential design - the two most basic signal CLK, rst_n (clock, reset), there must be some children's shoes can speak without rst_n, is can not, but why, make the code more robust is not very good, don't sit here to conquer CLK, rst_n writing:
First to tell me the timescale, because want to simulate must first time unit, and the best in the Testbench uniform unit of time, and not defined in the project code, because different module if time units may bring some problems for the simulation, and timescale itself has no effect on comprehensive is the actual circuit, ` timescale ns/1 ps said per unit time is 1 ns simulation, precision of 1 ps,
CLK generally there are three types of writing:
The purpose of the above three kinds of code to generate system clock, to the CLK after an initial value, repeated execution: once every 10 ns flip CLK, resulting in a cycle of 20 ns, 50 MHZ frequency square wave signal, the first, two kinds of basic similar, and the third is simpler, less an initial, in always initialized,
Three methods all without exception, give CLK assign the initial value, because the signal for the default value of Z, if not initialise, after inverse Z, the clock has been in a state of high impedance Z, small classmate, generally selected the first one to see like,
According to the different methods of reduction, rst_n generally there are two types of writing:
The fpga relevant article: what is the fpga
