ARM instruction set (general instructions)
A, ARM instruction
1. The ARM assembly instructions (ARM)
An assembly instruction only corresponding to a single machine instruction
MOV R0, # 5=& gt; 010101...

Opcode: what kind of operation "instruction auxiliary operator
"MOV said mobile
The ADD said addition
.
Operand:
Results the operands: used to store the calculated results
Arithmetic operands:
The first operand
The second operand

The ADD R0, R1, R2

Command is used to "operation" : operator
The operand
2. Directive (by the compiler factory agreed, keil environment keil directive,
The gnu environment with gnu directive)

Int a=5;

=& gt;
A
DCD 5

3. The macro instruction (same as above, designated by the compiler vendors)

In the second ARM CMP and various conditions judgment
CMP R1, R2;=& gt; If R1==R2, R1, R2 result is 0,
XPSR. Z==1

//MOV R0 (xPSR. Z==1), # 250
MOVEQ R0, # 250
EQ "equal"=& gt; Check xPSR. Z==1
EQ=& gt;
Condition code meaning test mark (logo) in xPSR
EQ=Equal (Equal) Z==1
NE!=Not Equal (Not Equal) Z==0
CS/HS (unsigned number) & gt;=Carry Set (C==1)
Unsigned who or Same C==1
=
A. & gt;=b
A - b does not need to borrow,=& gt; A. & gt;=b
"Do not need to borrow" said do subtraction does not need to borrow
C==1
C==1 when do subtraction, not borrow,

CC/LO (unsigned number) & lt; Carry the Clear (C==0) C==0
Unsigned LOwer

A. & lt; B
A - b needs to borrow (C==0)

MI MInous (negative) N==1
A. & lt; B
A - b & lt; O (N==1)

PL Positive or Zero (negative) N==0
A. & gt;=b

V V Set (overflow) V==1

VC V Clear (no overflow) V==0

HI (unsigned number) & gt; Unsigned who (C==1) & amp; & (Z==0)
A. & gt; B
A - b & gt; 0
A - b didn't borrow (C==1) and the result is 0 (Z==0)

LS (unsigned) & lt;=unsigned Lower or Same (C==0) | | (Z==1)
A. & lt;=b
A - b & lt;=0

GE & gt;=signed Greater or Equql N==V
=

LT & LT; Less Than N!=V


GT & GT; Greater Than (N==V) & amp; & (Z==0)

LE & lt;=Less than or Equal (Z==1) | | (N!=V)

Three, the ARM shift
LSL # n
Logic, Logic Shift Left Left n,
Logic logical shift, whether left or right, empty, are filling 0
LSR # n
Logic moves to the Right n, Logic Shift Right

In out of the bit is 0,
LSL # n is equivalent to the original register values multiplied by 2 n
LSR # n is equivalent to the original register values divided by the number of 2 n

ASR # n arithmetic moves to the right n bit
Arithmetic shift, should not change its symbol,
Highest n a fill the sign bit values.

ASL # n no=& gt; LSL

ROR # n ROtate Right circulation Right
Move to the right of the n position, fill to the left,

RRX belt loop moves to the right one
With C (xPSR. C) that a


Type the Rs
A type for the displacement mode, such as: the LSL, LSR, ASR, ROR, RRX...
Low Rs offset registers, eight effectively, to move bit digits stored in Rs,
Such as:
MOV R1, # 8
LSL R1=& gt; Logical left eight,

Such as:
The ADD R0, R1, R2, LSR # 2
R1 + R2 & gt;> 2 - & gt; R0

Four, ARM instruction (UAL)
1. The ARM memory access instructions
In Memory, the Memory, "-" is used to transfer data between register

The data from memory - & gt; Register loading Loader
The data from the register - & gt; Storage Store

(1)
LDR {cond} {S} {B}/H Rd, & lt; Address & gt;
STR {cond} {B}/H Rd, & lt; Address & gt;

LDR loading, storage & lt; Address & gt; The contents of the Rd loaded into the register of
STR storage, the contents of the registers Rd, stored in the storage & lt; Address & gt; In
No instruction can be realized both directly transfer data, how to do? LDR is loaded, and then the STR store

Memory address is according to the byte code,
[0000] 0 x2000 - & gt; R1
Excuse me, are you load a byte, or two bytes, or 4 bytes?

NOTE:
A. B: a Byte Byte, H: Half word Half word (2 bytes), if omitted, the default value is 4 bytes
B/H decided to load/store how many bytes

S: Signed the address of the variable, as a symbol,
If there is no S is the address of the variable, as an unsigned,
Short - & gt; Long (B/H), a symbol, high fill all the sign bit,
If it is unsigned, high fill all 0

B. address to determine the way: the base register + offset
Must need to address values in a register in the
That is:
Address values
[Rn, offset] Rn + offset Rn values
[Rn, offset]! Rn + offset Rn value=Rn + offset
(Rn), the offset Rn Rn value=Rn + offset

[] said memory address values,
If you have! Or, offset, outside the [] said done, base the offset value of
The offset has the following three ways:
Immediately number:
Such as: LDR R1, [R0, # 0 x12]
[R0 + 0 x12] - & gt; R1
Register
[R0, such as: LDR R1, R2)
[] R0 + R2 - & gt; R1
Register and shift constant
[R0, such as: LDR R1, R2, LSL # 2]
[R0 + R2 & lt; & lt; 2) - & gt; R1

Example:
Char ch=0 x80 (1.1);//compile time or run time for ch allocate a memory space 0 x2000 0000
int a;//compile time or run time, for a distribution of a memory space 0 x2000 0004
A=ch;

MOV R0, # 0 x20000000;
MOV R1, # 0 x80
STRB R1, R0


LDRSB R3, R0

The ADD R2, R0, # 4
STR R3, (R2)

(1.2)
Unsigned char ch=0 x80;//compile time or run time for ch allocate a memory space 0 x2000 0000
int a;//compile time or run time, for a distribution of a memory space 0 x2000 0004
A=ch;

MOV R0, # 0 x20000000;
MOV R1, # 0 x80
STRB R1, R0


LDRB R3, R0

The ADD R2, R0, # 4
STR R3, (R2)

(1.3)
C language, a global variable int a=7;
The local variable int a=7;


//global variables are compile-time will need to determine the memory address
Int a=7;//Keil

A
DCD 7

//local variables is to run time determine its address
Int a=7;
MOV R0, SP;//the current address on the top of the stack, as the address of the variable a
SUB SP, SP, # 4//stack elements -

MOV R1, # 7
STR R1, R0
(2) register to access more
On a continuous memory address, register for multiple access,
Load the LDR more Multi

Register more load LDM Loader Multi
More storage register STM Store Multi

LDM {cond} & lt; Model & gt; Rn {! }, reglist
STM {cond} & lt; Model & gt; Rn {! }, reglist

A. this is two instructions by a register an Rn specifies a memory address,
Multiple address of memory, is a continuous increase, or continuous decline?
By & lt; Model & gt; To specify:
Note: in either mode, lower address are corresponding number low register
IA: Incrememt After () After each delivery address automatically increase (+ 4) & lt; -- -- -- -- --
DB: Decrement Before Before each delivery address automatically reduce (4) & lt; -- -- -- -- --
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