Interrupt register IER

IER [0] to logic 1, is it enter the interrupt is ready to receive data
IER [1] for the logic 1, is it into interrupt to send empty instruction
IER [2] for the logic 1, is it into receiving interrupt bus

The three is understand it,

CodePudding user response:

Is this your English preparation on
IER [0] to 1, when the FIFO received after the specified number of data raise the interrupt
IER [1] to 1, when need to send up all data and didn't sent data raise the interrupt
IER [2] to 1, open to receive interrupt line state, this description is not very detailed, needs to see the other relevant content just know, estimates that there are data starting interrupt or in receiving interrupt line state changes

CodePudding user response:

Upstairs, thank you for your advice, these two figure is all a function of IER, English foundation is bad, all wrong, now playing with philips SC16C654DB, a string of turn and function, less good information online, the website has no information, English foundation is bad, wrong, for it's control command to write wrong, big, ha ha, more can't do a lot more than English