Home > other > In zedboard board configuration ADAU1761 AD sampling, the collected signal turn negative half cycle
In zedboard board configuration ADAU1761 AD sampling, the collected signal turn negative half cycle
Time:10-03
Sine wave signal generator is given, from MIC interface LINN input, schematic diagram below
When I enter for the 2 k - 500 mv - 500 mv frequency sine wave, the collected digital quantity is like this:
Negative half cycle of the waveform will turn up, ever thought that is because the negative voltage to the inside of the system when do the processing of the complementary code, so when I change the parameters of the input signal and the input of 0-1 v sine wave (no load voltage in the signal) at this time, to capture again, found the situation still exists, the negative half cycle signal will still turn up, the result is shown below:
So I feel not because of collecting negative negative half cycle of voltage waveform flip up, now very lost, don't know where is wrong, please teach the great god, The way I configuration is single-ended input, and then directly through the mixer, without PGA, Part of the register configuration is as follows: AudioWriteToReg (R5_RECORD_MIXER_LEFT_CONTROL_1, 0 x00);//LINNG 0 dB gain X0b AudioWriteToReg (R4_RECORD_MIXER_LEFT_CONTROL_0, 0); X0b AudioWriteToReg (R6_RECORD_MIXER_RIGHT_CONTROL_0, 0); AudioWriteToReg (R7_RECORD_MIXER_RIGHT_CONTROL_1, 0 x00);//RINNG 0 dB gain
Hope, every comment, little women appreciate!
CodePudding user response:
Add: zedboard is xilinx zynq7000 series is a product of the fpga development board
CodePudding user response:
This is the need to have symbol data, reference voltage to the middle, is negative to do well