Don't like to write in the ISE own editor verilog program, with other editors wrote a fifo fifo module, v, and then write a test program test_fifo, v, and then put them in the same project, but found a glum problem: the two files are. V file, each join test_fifo. V ISE all the test files as a formal integrated module, comprehensive will go wrong, how to solve this problem, please?