FPGA, such as frequency measurement precision, in view of the FPGA mathematical operation is not very friendly, the end result of this program is only the clock signal and the signal being measured in the gate time pulse count,

The module test_f (
Input clk_50M//define the system clock 50 m
The input signal,//be measured signal
//the output wire uart count for a serial port to send, omit this part, this is no need for

);


The parameter GATE_TIME=49 _999_999;

Wire [31:0] CNTCLK;//the system clock count
Wire [31:0] CNTSIG;//measured signal count

Reg=28 '[27:0] cnt1 d0;//produce 1 s gate signal counter reg
Reg gate=1 'b0;//gate signal

Reg signal_r0=1 'b0;
Reg signal_r1=1 'b0;
Reg signal_r2=1 'b0;
Reg signal_r3=1 'b0;

Reg gatesyn=1 'b0;//gate after the synchronization with square wave signal
Reg gatesyn1=1 'b0;//synchronous gate signal delay a beat

Reg=32 '[31:0] cnt2 d0;
Reg=32 '[31:0] cnt2_r d0;

Reg=32 '[31:0] cnt3 d0;
Reg=32 '[31:0] cnt3_r d0;

Wire signal_pose signal_nege;

Always @ (posedge clk_50M) begin
If (cnt1==GATE_TIME) begin
Cnt1 & lt; D0=28 ';
Gate & lt;=~ gate;//produce 1 s gate signal
End
The else begin
Cnt1 & lt;=cnt1 + 1 'b1;
End
End

Always @ (posedge clk_50M) begin//testing input signal of the rising or falling, gate time synchronization with square wave under test can be
Signal_r0 & lt;=signal;
Signal_r1 & lt;=signal_r0;//will play two pat the external input square-wave
Signal_r2 & lt;=signal_r1;
Signal_r3 & lt;=signal_r2;
End

The assign signal_pose=signal_r2 & amp; ~ signal_r3;
The assign signal_nege=~ signal_r2 & amp; Signal_r3;


Always @ (posedge clk_50M)//synchronize the gate signal and square wave under test, guarantee a gate contains an integer square wave cycle
The begin
If (==1 'signal_pose b1) begin
Gatesyn & lt;=gate;
End

Gatesyn1 & lt;=gatesyn;//will play a clap, gate after the synchronization signal is used to capture the edge gate signal
End

The assign gate_start=gatesyn & amp; ~ gatesyn1;//said gate start time
The assign gate_end=~ gatesyn & amp; Gatesyn1;//gate end

//count the system clock
Always @ (posedge clk_50M)
The begin
If (==1 'gate_start b1) begin
Cnt2 & lt; D1=32 ';
End
Else if (gate_end==1 'b1) begin
Cnt2_r & lt;=cnt2;//to save the result in cnt2_r, and counter reset
Cnt2 & lt; D0=32 ';
End
Else if (gatesyn1==1 'b1) begin//within the gate count system clock cycle
Cnt2 & lt;=cnt2 + 1 'b1; End
End

//count for testing the clock

Always @ (posedge clk_50M)
The begin
If (==1 'gate_start b1) begin
Cnt3 & lt; D0=32 ';
End
Else if (gate_end==1 'b1) begin
Cnt3_r & lt;=cnt3;//to save the result in cnt3_r, and counter reset
Cnt3 & lt; D0=32 ';
End
Else if (gatesyn1==1 'b1 & amp; & Square_nege==1 'b1) begin//within the gate count for the square wave cycle count (the number inside the gate falling edge of the square wave)
Cnt3 & lt;=cnt3 + 1 'b1;
End
End

The assign CNTCLK=cnt2_r;
The assign CNTSIG=cnt3_r;