For now, study the FPGA has been for some time, also is almost more than a year, and to my own position is senior beginners, some simple logic function implementation, some communication interface, etc., also can come, but, as their away gradually in the FPGA on the road, the ensuing problems also arrive,
Is a problem bothering me for a long time now, I have compiled the same when a program downloaded to the board, the effect would be different, I am currently doing a project image acquisition and processing, there are flowers image screen, flickering phenomenon, and this kind of phenomenon is random, recompile, sometimes problems may be gone,
Online to find a lot of data, some say sequence without adding constraints, some say it's layout and wiring problems, I also searched for this, I feel there is no add timing constraints, but this really lack, beside the person did not ask,
So, who is a great god saw this post, hope you can help the younger brother, provide information, direction, is there any information such as recommended, on demand, thank you very much

CodePudding user response:

Play with fpga is ace!

CodePudding user response:

Image screen, flashing, we play stn32, tend to consider the power do not clean, your power is directly DCDC? Don't think will have better after a ", or by a LC filter,

CodePudding user response:

Some initial state of signal pin look limited

CodePudding user response:

The

reference blackout reply: 3/f

some of the initial state of signal pin look limited

Well, brother, your description to understand adverse
You mean the unused pins, on the whole set to pull or next?
Single chip microcomputer to do so effectively, all output mode, and then the drop-down,
But the FPGA chip is different, is that right

CodePudding user response:

The timing of the report, then

CodePudding user response:

reference 4 floor zhouml_msn response:

Quote: reference 3 floor blackout response:

some of the initial state of signal pin look limited

Well, brother, your description to understand adverse
You mean the unused pins, on the whole set to pull or next?
Single chip microcomputer to do so effectively, all output mode, and then the drop-down,
But the FPGA chip is different, so is it

: no, I said the initial state, if the design didn't set IO mouth of initial state, the FPGA is started corresponding IO port state may be unknown,
A Reset function can be used to troubleshoot a is the initial state of the IO port,

CodePudding user response:

Thanks for your reply, I don't know how to separate reply, the power of the board is no problem, layer upon layer filter, the image is fine for simple display, is to add some image processing, the problems, and the FPGA after power on the default is 0,

CodePudding user response:

Could it be poor contact peripherals and interface card? Lead to cable or affected the line of control signal,