Sent in several BBS posts all nobody to hope this help thank you very much
Pci @ 0 x10180000 {
Compatible="arm, versatile - pci - hostbridge", "pci";
Reg=& lt; 0 x10180000 0 x1000 & gt;;
Interrupts=& lt; 8 0 & gt;;
Bus - ranges=& lt; 0 0 & gt;;

# address - cells=& lt; 3 & gt;
# size - cells=& lt; 2 & gt;;
Ranges=& lt; X42000000 0 0 0 x80000000 0 x80000000 0 0 x20000000
X02000000 0 0 0 xa0000000 0 xa0000000 0 0 x10000000
0 x01000000 0 0 x00000000 xb0000000 0 0 0 x01000000 & gt;;
};
I want to ask is about the pcie bus address mapping relationship between the CPU and recently began to learn pcie with vague concept according to my understanding to reg=find information & lt; 0 x10180000 0 x1000 & gt;; Its own address should be the 0 x10180000 pcie bus with other devices and equipment in the reg device tree address like the CPU can access directly to the pcie seems to need to address translation ranges=& lt; X02000000 0 0 0 xa0000000 0 xa0000000 0 0 x10000000 from bus so a0000000 a0000000 mapped to the CPU address? I want to visit the resources should be in the reg a0000000 + 10180000? But mapping specific length is only 10000000? Online about the less anyone help me
In addition for the processor of non-x86 pcie mapped to IO space of the CPU and memory space of the two functions are the same?