Now is trying to realize three fifo communication, that is, to send and receive 96 byte directly, you can now send, but receive there with logic analyzer test only received 64 byte, and there is a 446 us delay without delay (code), send the uncertain is perfect or not,

Send the configuration
Void TX_Mode (void)
{
NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + CONFIG, 0 x02);//shutdown mode
NRF24L01_CE_0 ();
NRF24L01_Write_Buf (NRF_WRITE_REG + TX_ADDR (uint8_t *) TX_ADDRESS, TX_ADR_WIDTH);//write TX node address
//NRF24L01_Write_Buf (NRF_WRITE_REG + RX_ADDR_P0 (uint8_t *) RX_ADDRESS, RX_ADR_WIDTH);//set the TX node address, mainly in order to make to ACK
NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + SETUP_AW, 0 x01);//address a 3 bytes

NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + EN_AA, 0 x00); Answering//close the channel 0
NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + FEATURE, 0 x01);//enabled command W_TX_PAYLOAD_NOACK
NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + SETUP_RETR, 0 x00);//enabled command W_TX_PAYLOAD_NOACK

NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + RF_CH, 1);//set the RF channel, channel 1-125, to avoid other signal interference, choose not commonly used, usually the more the greater the interference between

//NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + RF_SETUP, 0 x0f);//set the TX launch parameters, 0 db gain, 2 MBPS, low noise gain
NRF24L01_NRF_WRITE_REG (x07 NRF_WRITE_REG + RF_SETUP, 0);//set the TX launch parameters, 0 db gain, 1 MBPS, low noise gain
//NRF24L01_NRF_WRITE_REG (x27 NRF_WRITE_REG + RF_SETUP, 0);//set the TX launch parameters, 0 db gain, 250 KBPS, low noise gain

//NRF24L01_NRF_WRITE_REG (x0e NRF_WRITE_REG + CONFIG, 0);//configuration parameters of basic working pattern; PWR_UP EN_CRC, 16 bit_crc, receiving mode, open all interrupts
NRF24L01_NRF_WRITE_REG (x0a NRF_WRITE_REG + CONFIG, 0);//receiving mode, open all interrupt, no CRC
NRF24L01_CE_1 ();//CE is high, after 10 us start sending
Delay1 (0 XFFFF);//CE to pull up a period of time to send the pattern
}
Receiving configuration
Void RX_Mode (void)
{
NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + CONFIG, 0 x02);//shutdown mode

NRF24L01_CE_0 ();
NRF24L01_Write_Buf (NRF_WRITE_REG + RX_ADDR_P1 (uint8_t *) RX_ADDRESS, RX_ADR_WIDTH);//write RX node address


NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + SETUP_AW, 0 x01);//address a 3 bytes
NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + FEATURE, 0 x01);//enabled command W_TX_PAYLOAD_NOACK
NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + EN_AA, 0 x00); Answering//close the channel 0

NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + EN_RXADDR, 0 x02);

//enabled channel 0 receives address
NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + RF_CH, 1);//set the RF communication frequency
NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + RX_PW_P1 RX_PLOAD_WIDTH);//select the valid data width of channel 0

//NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + RF_SETUP, 0 x0f);//set the TX launch parameters, 0 db gain, 2 MBPS, low noise gain
NRF24L01_NRF_WRITE_REG (x07 NRF_WRITE_REG + RF_SETUP, 0);//set the TX launch parameters, 0 db gain, 1 MBPS, low noise gain
//NRF24L01_NRF_WRITE_REG (x27 NRF_WRITE_REG + RF_SETUP, 0);//set the TX launch parameters, 0 db gain, 250 KBPS, low noise gain

//NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + CONFIG, 0 x0f);//configuration parameters of basic working pattern; PWR_UP EN_CRC, 16 bit_crc, receiving mode
NRF24L01_NRF_WRITE_REG (x0b NRF_WRITE_REG + CONFIG, 0);//receiving mode, no CRC

NRF24L01_CE_1 ();//CE for high, into receiving mode
}
Void NRF24L01_RxPacket_96bit (uint16_t * rxbuf)
{
Uint8_t status, sta, I, j, data1, fifo_status;
Uint16_t data;
Uint8_t num=0;
NRF24L01_CE_1 ();
While (NRF24L01_IRQ!=0);//waits to receive complete
NRF24L01_CE_0 ();
The sta=NRF24L01_Read_Reg (STATUS);//read status register values
If (sta& RX_OK)//received data
{
Fifo_status=NRF24L01_Read_Reg (fifo_status);
while(! (fifo_status & amp; 0 x01))
{
NRF24L01_CE_0 ();
NRF24L01_CSN_0 ();//can make SPI transfer
SPIx_ReadWriteByte (RD_RX_PLOAD);//send the register values (position), and reads the status value
for(j=0; j{
Data1=SPIx_ReadWriteByte (0 XFF);//read data
data=https://bbs.csdn.net/topics/(data1 <8);
* rxbuf++=data;
* rxbuf++=0;
}
NRF24L01_CSN_1 ();//close the SPI transfer
NRF24L01_CE_1 ();
Fifo_status=NRF24L01_Read_Reg (fifo_status);
}
NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + STATUS, the sta);//remove TX_DS or MAX_RT interruption sign
NRF24L01_NRF_WRITE_REG (FLUSH_RX, 0 XFF);//remove RX FIFO registers
}
}
Void NRF24L01_TxPacket_96bit (uint16_t * txbuf)
{
Uint8_t sta, status, j, I, data, fifo_status;
Uint16_t data1, data2;
//NRF24L01_NRF_WRITE_REG (FLUSH_TX, 0 XFF);//remove the TX FIFO registers
NRF24L01_NRF_WRITE_REG (NRF_WRITE_REG + STATUS, 0 x20);//remove TX_DS or MAX_RT interruption sign
Fifo_status=NRF24L01_Read_Reg (fifo_status);

If ((fifo_status & amp; 0 x10))
{
NRF24L01_CE_0 ();
for(i=0; i<3; I++)
{
NRF24L01_CSN_0 ();
Status=SPIx_ReadWriteByte (W_TX_PAYLOAD_NOACK);//send the register values (position), and reads the status value
for(j=0; j{
Data1=* txbuf++;
Data2=* txbuf++;
data=https://bbs.csdn.net/topics/(uint8_t) ((data1 and data2)> 8);
SPIx_ReadWriteByte (data);//write data
}
NRF24L01_CSN_1 ();//close the SPI transfer
}
NRF24L01_CE_1 ();//start sending
}
While (NRF24L01_IRQ!=0);//waiting to send complete
Delay_us (7);//delay_us (500);
}