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CPLD design 8-way counter channel (ask)

Time:10-06

(1) the use of CPLD chip design counter channel 8 road, every road length counter 16;
(2) each counter should have CLK (count pulse income) and OUT (output) and GATE (gating) three input/output end (see 8253 a timer/counter chip),
(3) of four channels should possess the function of the workings of a 8253 a 0, the other four channel should have the function that the workings of a 8253 a 3,

(4) the circuit should be designed with 51 single-chip microcomputer bus (sixteen 8-bit data bus, address bus and the read/write control line), 8 channel for addressing three address code and the circuit of the chip choose CS signal, (5) verify the circuit function, physical or circuit simulation,

CodePudding user response:

There are many counters on pudn demo
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