The system clock is 50 m, should produce high level 10 us, why is behind all high level???????
The module changshi3 (u, pulse, CLK, RST, huibao);
The input CLK, RST, pulse, u; ?
The output huibao;
Reg huibao;
Reg [3-0] state;
Reg 31:0 CNT, cnt1, cnt2, cnt3;
Parameter A='d0, B=' d1, C='d2, D=d3, E=' F=d4, d5, G='d6, H=' d7;
Always @ (posedge CLK or negedge RST)
if(! RST)
The begin
State<=A; Huibao<=0; Cnt<=0;
Cnt1 & lt;=0; Cnt2 & lt;=0;
End
The else
Case (state)
A: the begin the if (u==0) state<=A;
Else if (pulse)
State<=B;
The else state<=A; End
B: the begin the if (u==0) state<=A;
The else cntif(! Pulse)
State<=C;
The else
State<=B; End
C: the begin the if (u==0) state<=A;
Else if (cnt>
=124)The begin state<=D; Cnt1 & lt;=cnt1 + 1; End
The else state<=A; End
D: if (u==0) state<=A;
Else if (pulse==0)
State<=D;
The else state<=E;
E: if (u==0) state<=A;
Else if (cnt1 & lt; 2499)
State<=F;
The else state<=A;
F: begin the if (u==0) state<=A;
The else cnt2 & lt;=cnt2 + 1;
If (pulse==1)
State<=F;
The else
State<=G; End
G: the if (cnt2 & gt;
=124)The begin state<=H; Huibao<=1; End
The else state<=F;
H: if (cnt3==499)
The begin
Huibao<=0; State<=A;
End
The else state<=G;
Default: state<=A;
Endcase
Always @ (posedge CLK or negedge RST)
if(! RST)
Cnt3 & lt;=0;
Else if (huibao==1)
The begin
If (cnt3==499)
Cnt3 & lt;=0;
The else begin cnt3 & lt;=cnt3 + 1; End end
Endmodule