Use bank32, bank33 DDR and mig nuclear connection pin for pin, DDR use level 1.35 v, set up IP option is 1.35, and a simple mig driver, at the top of the binding of a clock pin, compile time comprehensive, in the second step map error, said the pin level is not compatible, (this project code on the vivado verified, can run, is equivalent to the project to build a) on the ise,

Error on binding of pins are submitted to the IP to the wrong, never useful LVCMOS18., the level come from?
ERROR: PhysDesignRules: 2407 - Unsupported IO configuration for comp ddr3_dq & lt; 0 & gt; .
The use of input pin DCITERMDISABLE is not compatible with The IO standard
LVCMOS18.
ERROR: PhysDesignRules: 2407 - Unsupported IO configuration for comp ddr3_dq & lt; 9 & gt; .
The use of input pin IBUFDISABLE is not compatible with The IO standard LVCMOS18.

ERROR: PhysDesignRules: 2407 - Unsupported IO configuration for comp ddr3_dq & lt; 9 & gt; .
The use of input pin DCITERMDISABLE is not compatible with The IO standard
LVCMOS18.

CodePudding user response:

Too long used ISE, you check in the ISE DDR IP level constraints, requires the user to create, rather like vivado automatically generated level constraints

CodePudding user response:

ISE of mig nuclear create and vivado is same, also is binding a pin, verify below to automatically generate level standard, look at the is right, also did not appear lvcmos18 level standard