Home > other >  Verilog HDL string and converter setting signal problem
Verilog HDL string and converter setting signal problem

Time:10-07

I have a string and converter module, the purpose is to put a cable on the single-ended serial data into parallel data,
The question now is: due to a hardware circuit is only a line data input and no other line, how can I in the wires can not only realize the setting and can realize the data transmission?
  • Related