7000 series, zynq vivado block design called clock wizard to produce multiple clock output to the PL, clock input from PL side MRCC wizard, at the same time the output to PL internal logic and ordinary I/O or use BUFG BUFH driver (the same bank or bank), but at the time of implementation errors, or an error when using the bitstream,
Want to ask everybody zynq clock output to the normal I/O requirements? Input needed to use the clock pin, so the output? And what is the relationship between the clock domain? Whether specific says it when the clock wizard needs output to the internal logic and external I/O at the same time need to be set?