Home > other >  Error (10170) : Verilog HDL syntax Error at myclock. V (157) near the text "always". e
Error (10170) : Verilog HDL syntax Error at myclock. V (157) near the text "always". e

Time:10-09

Implore you to see the Quartus2 file which went wrong? (number of electricity experiment) always @ (posedge clk_25khz) begin the if (scan_led_com & lt; 7)
Scan_led_com=scan_led_com + 1;
The else scan_led_com=0;
End
Always @ (posedge clk_25khz)//2.5 KHz
The begin case (scan_led_com)
3 'b000: shuju=shi2;
3 'b001: shuju=shi1;
3 'b010: shuju=fen2;
3 'b011: shuju=fen1;
3 'b100: shuju=miao2;
3 'b101: shuju=miao1;
Default: shuju=4 'b0000;
Endcase
Case (scan_led_com)//loop scanning eight leds, a total of 3 'b000: seg_com=8' b00000001 anode;
=8 '3' b001: seg_com b00000010;
=8 '3' b010: seg_com b00000100;
=8 '3' b011: seg_com b00001000;
=8 '3' b100: seg_com b00010000;
=8 '3' b101: seg_com b00100000;
=8 '3' b110: seg_com b01000000;
=8 '3' b111: seg_com b10000000;
Default: seg_com=8 'b00000000; Endcasecase (shuju)//display decoder, light pgfedcba section, low level 4 'b0000:seg_data=https://bbs.csdn.net/topics/8' effective b11000000;//0 4 'b0001:seg_data=https://bbs.csdn.net/topics/8 b11111001;//1 4 'b0010:seg_data=https://bbs.csdn.net/topics/8 b10100100;//2, 4 'b0011:seg_data=https://bbs.csdn.net/topics/8 b10110000;//3 4 'b0100:seg_data=https://bbs.csdn.net/topics/8 b10011001;//4, 4 'b0101:seg_data=https://bbs.csdn.net/topics/8 b10010010;//5 4 'b0110:seg_data=https://bbs.csdn.net/topics/8 b10000010;//6 4 'b0111:seg_data=https://bbs.csdn.net/topics/8 b11111000;//7, 4 'b1000:seg_data=https://bbs.csdn.net/topics/8 b10000000;//8 4 'b1001:seg_data=https://bbs.csdn.net/topics/8 b10010000;//9
Default: seg_data=https://bbs.csdn.net/topics/8 'b11111111;
Endcase
endendmodule
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