The FPGA test files inside this code can have what effect? Single out one can understand, don't-CodePudding

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The FPGA test files inside this code can have what effect? Single out one can understand, don't

Time：10-09

Initial the begin
RST=1;
CLK=0;
# 100;
RST=0;
End
Always # 5 CLK=~ CLK;

endmodule

CodePudding user response:

First reset again five cycle CLK signal flip, output a CLK, is actually a CLK module