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For help: the FPGA based on DDS signal generator to generate sine, square wave, sawtooth wave

Time:10-10

Have a headache and old long editor can pass, but cannot achieve function, corresponding mif ROM another generation,
The library ieee.
Use the ieee. Std_logic_unsigned. All;
Use the ieee. Std_logic_1164. All;
Use the ieee. Std_logic_arith. All;

The entity XHFASH is
The port (RST: in std_logic;
CLK: in std_logic;
M, k0, p0: in std_logic; - mode, frequency modulation, phase shift
Quot: out std_logic_vector 7 downto (0));
End XHFASH;
Architecture arc of XHFASH is
Signal clk1: std_logic;
Signal sel: std_logic_vector downto 0 (1) :="00";
Signal q_sin: std_logic_vector (7 downto 0); - sine signal
Signal q_square: std_logic_vector (7 downto 0); - square wave signal
Signal q_sawtooth: std_logic_vector (7 downto 0); - the sawtooth wave signal
Signal counter, p1: std_logic_vector 7 downto (0) :="00000000";
Signal k1: std_logic_vector 7 downto (0) :="00000001";
Signal phase_shift: std_logic_vector (7 downto 0);

Component sin - this is the sine wave
The port (
Address: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Clock: IN STD_LOGIC:='1';
Q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
End component of sin;

Component square - this is the square wave
The port (
Address: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Clock: IN STD_LOGIC:='1';
Q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
End component square;

Component sawtooth -- the sawtooth
The port (
Address: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Clock: IN STD_LOGIC:='1';
Q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
End component sawtooth.
The begin
U1: sin port map (address=& gt; Phase_shift, q=& gt; Q_sin, clock=& gt; Clk1);
U2: square port map (address=& gt; Phase_shift, q=& gt; Q_square, clock=& gt; Clk1);
U3: sawtooth port map (address=& gt; Phase_shift, q=& gt; Q_sawtooth, clock=& gt; Clk1);


The process (CLK)
Variable n1: integer range 0 to 2; - 1953
The begin
If CLK 'event and CLK=' 1 'then
If n1=2 then n1:=0; - 1953
Elsif n1 & lt; 2 then
N1:=n1 + 1; - 1953
Elsif n1 & gt; 1 then
Clk1 & lt;='1'. - 977
The else clk1 & lt;='0'.
end if;
end if;
End the process. - clk1=25600 hz

The process
The begin
Wait until clk1 'event and clk1=' 1 '.
If RST='0' then
K1 & lt;="00000001"; P1 & lt;="00000000";
end if;
If K0='0' then
Elsif K1="00001010"
Then K1 & lt;="00000001";
The else
K1 & lt;=K1 + 1;
end if;
If P0='0' then
P1 & lt;=(P1 + 16;
end if;
End the process.

The process
The begin - accumulator description
Wait until clk1 'event and clk1=' 1 '.
If RST='0' then
Counter<=(others=& gt; '0');
The else counter<+ K1=counter;
end if;
End the process.
- phase adder description
The process
The begin
Wait until clk1 'event and clk1=' 1 '.
If RST='0' then
Phase_shift & lt;=(others=& gt; '0');
The else phase_shift & lt; + p1=counter;
end if;
End the process.
- data selector;
The process
The begin
Wait until clk1 'event and clk1=' 1 '.
If M='0' then
Elsif sel="10"
Then sel<="00";
The else
Sel<=sel + 1;
end if;
Case sel is
When "00"=& gt; Quot<=q_sin;
When "01"=& gt; Quot<=q_square;
The when OTHERS=& gt; Quot<=q_sawtooth;
End a case;
End the process.
End the arc;

CodePudding user response:

Problem solved, clock...

CodePudding user response:



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