Is existing in the conventional CPU instruction cache queue, used to waiting for CPU execution? (in addition to the Cache, controller of microinstruction queue)

Still say each have to IR to Cache read the next instruction in advance?

CodePudding user response:

Generally two levels of assembly line are two instructions to perform prefetching, interrupted again

CodePudding user response:

In general, in the modern CPU instructions should have at least three status, value, decoding and execution, there will be multiple instructions in assembly line, which is why the cause of the assembly line,