Everybody is good, our laboratory has developed an experiment board, the main chip is virtex - 6 LX240T (design similar ML605 development board), the front-end ports design is the FPGA + 88 e1111, but the design of two such front-end ports, one of the front-end ports (the front-end ports and ML605 development board so) has the tests pass, can communicate with PC normally, but another so front-end ports (new design) cannot communicate with PC, excuse me the great spirit: 1. Is there any way to make new designs so normal communication? 2. How can you make two so work at the same time?
So far I have done the following:
1. With ML605 development board so consistent that so, through the lwip protocol testing, the underlying code written by senior laboratory, through!
2. For new design, so, I to modify the first pin constraints of the underlying code, will originally constraints to the first signal on PHY chip pins, constrain to the second PHY chip, regenerate the bit stream file, there is an error, a great god, please help!

CodePudding user response:

The two so try switching

CodePudding user response:

QQ; 1018550491

CodePudding user response:

Hello, can put the PC communication with normal development board show me the code to send me? I am in this,