Do the audio processing, audio processing data using DMA ping pong buffer write data to the I2S FIFO, here I have two questions:
1: the DMA using circulation mode, move the ping buffer after automatically move pong buffer, cycling, I understand it, the DMA move speed should be much faster than I2S playback speed, DMA control rehandling itself will have a timing problem?
2: the DMA move ping buffer, CPU write pong buffer, so the DMA in move ping buffer, take the bus, how CPU can write pong buffer, write to also want to through the bus!!!!!

CodePudding user response:

I understand the DMA hardware implementation, there is a certain bus, but he doesn't need the intervention of the CPU, also don't need a lot of CPU operations, so soon, as for the transfer speed also see who is wearing with it, depends on the peripherals, if mem to mem that fairly quickly

CodePudding user response:

There have a rate control to be understood, the DMA handling speed is controlled by the rate at which data is I2S read/take, the rate at which the DMA is always consistent with the rate of I2S, I2S read rate is controlled by the clock frequency, so as long as the configured I2S clock frequency, can control the play/reflection rate,
Rate, and the top of the physical memory, speaking, reading and writing with alsa there are reading and writing control, such as playing when they first obtain writable memory size, if less than the amount of data, will wait for the DMA data pump away before you write, and vice versa,