Want to learn the use of the PCIe, recently have a P2020RDB - PCA development board, board installed SiI3132 PCIe SATA controller as an EP equipment, P2020 on-chip integration PCIe controller as RC, established in accordance with the CodeWarrior wizard bare-metal engineering, initialize the content is as follows:
1, MMU configuration, could be divided into PEX2 0 x80000000-0 x9fffffff space
2, the configuration of LAW, could be divided into PEX2 0 x80000000-0 x9fffffff space
3, configuration PCIe memory-mapped register:
OUTBOUND ATMU configuration is as follows, each ATMU allocated 16 MB of space:
Corresponding address 0 PEXOBAR1: x81000000
Corresponding address 0 PEXOBAR2: x82000000
Corresponding address 0 PEXOBAR3: x83000000
Corresponding address 0 PEXOBAR4: x84000000

Corresponding address 0 x00000000 PEXOTAR0:
Corresponding address 0 x01000000 PEXOTAR1:
Corresponding address 0 PEXOTAR2: x02000000
Corresponding address 0 PEXOTAR3: x03000000
Corresponding address 0 x04000000 PEXOTAR4:

Corresponding address 0 x00000000 PEXOTEAR0:
Corresponding address 0 x00000000 PEXOTEAR1:
Corresponding address 0 x00000000 PEXOTEAR2:
Corresponding address 0 x00000000 PEXOTEAR3:
Corresponding address 0 x00000000 PEXOTEAR4:

The configuration of the INBOUND ATMU slightly,

4, the configuration of the RC type1 register configuration space, including
Corresponding address 0 PEXCSBAR: x08000000
The Memory Base: correspondence address 0 x00000000
The Memory Limit: correspondence address 0 x03ffffff
Prefetchable Memory Base: the corresponding address 0 x04000000
Prefetchable Memory Limit: the corresponding address 0 x04ffffff
Corresponding address 0 x00000000 Prefetchable Base Upper 32:
Prefetchable Limit Upper 32: correspondence address 0 x00000000
Bus # 0, secondary bus no. 1, downstream bus no. 9

5, query LTSSM register can be found link-state 0 x16, has entered the state L0,
And register configuration of EP type0 configuration space, the
Corresponding address 0 BAR0: x02000000
Corresponding address 0 BAR1: x03000000
BAR2: correspondence address 0 x04000000

Query P2020 handbook found that software to emit TLP things, should be configured first OUTBOUND ATMU, then PEXOWAR RTT or WTT write values to trigger the PCIe bus send corresponding memory/configuration, speaking, reading and writing,
In trying to access LAW assigned PCIE address space (such as 0 x82000000), development environment prompted: Error Reading the Memory run and fly, my question is as follows:
1, in an uninitialized PCIe relevant register, attempting to access the LAW assigned PCIe address space also appears the above error, when configured ATMU after unit is still unable to access, whether I configured incorrectly? Or access to the above address forms is wrong?
2, through the OUTBOUND ATMU has launched a PCIe memory read/write transaction process? Whether to fill in the data in a certain PEXOBAR first, then write PEXOWAR RTT or WTT domain to trigger the PCIe affairs to send?
3, began to doubt is the problem of environment configuration, try to change the LAW in the address space of the corresponding PEX2 to map to the NOR FLASH, it is found that can be read to the address of the data, basic ruled out the possibility,

Bother your guidance, small white to don't know much about

CodePudding user response:

Hello, your P2020 development board still in? Want to discuss with you, I also in debugging a P2020 development board, in addition, if possible, could you pay the way, to borrow your development board, thank you, my phone: 135-2180-2157, thank you.