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Sx1278 wireless ad-hoc network module 433 m grasp synthetic what tool points what channel

Time:10-20

Anyone with sx1278 graduation design ad-hoc network do now just do a point-to-point has not divided channel consider using time-division multiple access request caught display data to do have a great god

CodePudding user response:

# include & lt; Iostm8s103f3. H>
# include "My_type. H"
# include "is the main. H"
# include "sx1276 - LoRa. H"

Void UART1_init (void)
{
UART1_CR2=0;
UART1_SR=0;
UART1_CR1=0;
UART1_CR3=0;
UART1_BRR2=0 x00;//set the baud rate 19200
UART1_BRR1=0 x1a;//8 m/2400=0 x1a0
UART1_CR2=0 x00;//
}
Void TIM1_init (void)
{
TIM1_PSCRH=0 x1f;//8 m system clock frequency by preassigned f=FCK/(PSCR + 1)
TIM1_PSCRL=0 x3f;//PSCR=0 x1f3f, f=8 m/(0 x1f3f + 1)=1000 hz, counting each cycle 1 ms
TIM1_ARRH=0 x00;//auto reload register ARR=0 x01f4=500
TIM1_ARRL=0 x64;//every count 100 times generate an interrupt, which is 100 ms
TIM1_IER=0 x01;//allows you to update the interrupt
TIM1_CR1=0 x01;//counter is enabled, began to count
}

Void EXTI_init (void)
{
EXTI_CR1=0 x40;////PD mouth rising along the trigger interrupt DIO0 is L at ordinary times, received a packet of data and the CRC, right DIO0 into H
}

Void Sx1276EV_IO_Inital ()
{
//S_Tx
PC_DDR_DDR1=0;//S_Tx
PC_CR1_C11=1;////PULL - UP - INPUT
PC_CR2_C21=0;//
//S_Rx
PC_DDR_DDR1=0;//S_Rx
PC_CR1_C11=1;////PULL - UP - INPUT
PC_CR2_C21=0;//
//S_BW10
PA_DDR_DDR1=0;//
PA_CR1_C11=1;////PULL - UP - INPUT
PA_CR2_C21=0;

//S_BW62
PA_DDR_DDR2=0;//
PA_CR1_C12=1;////PULL - UP - INPUT
PA_CR2_C22=0;

//S_BW125
PB_DDR_DDR3=0;//
PB_CR1_C13=1;////PULL - UP - INPUT
PB_CR2_C23=0;

//S_FSK
PB_DDR_DDR7=0;//
PB_CR1_C17=1;////PULL - UP - INPUT
PB_CR2_C27=0;
}

Void KeyRead (void)
{
U8 ReadData;
Flg_S_BW10=1;//S_BW10;//
Flg_S_BW62=1;//S_BW62;//
Flg_S_BW125=0;//S_BW125;//
Flg_S_FSK=1;//S_FSK;//
Flg_S_Tx=0;//S_Tx;
Flg_S_Rx=1;//S_Rx;
ReadData=https://bbs.csdn.net/topics/Flg ^ 0 XFF.
Trg=ReadData & amp; (ReadData ^ Cont);
Cont=ReadData;
Cont & amp;=0 x1f;
If ((Cont.=ContBak) & amp; & (ContBak!=0 XFF))
WWDG_CR=0 x8f;//STM8 software reset the whole system
}

Void SX1276_Parameters_Select ()
{
ContBak=Cont;
If ((Cont& 0 x10)==cTx_Statue)
{

Tx_phase=SetTx_Parameters;
}
The else
{

Rx_phase=Rx_Parameters_Set;
}

The switch (Cont& 0 x0f)
{
Case 1:
/BW choose * * * * * * * * * * * * */
Gb_BW=1;/BW/10.4 K
//gb_BW=2;/BW/15.6 K
//gb_BW=3;/BW/20.8 K
//gb_BW=4;/BW/31.2 K
//gb_BW=5;/BW/41.7 K
//gb_BW=6;/BW/62.5 K
//gb_BW=7;//125 KHZ BW
/* * * * end of BW choose * * * * * * * * */

/* * * * * * * SF, choose * * * * * * * * */
//gb_SF=0;//SF=6; 64 chips/symbol
//gb_SF=1;//SF=7; 128 chips/symbol
//gb_SF=2;//SF=8; 256 chips/symbol
//gb_SF=3;//SF=9; 9 512 chips/symbol
Gb_SF=4;////SF=10; 1024 chips/symbol
//gb_SF=5;////SF=11; 2048 chips/symbol
//gb_SF=6;//SF=12; 4096 chips/symbol
/* * * * end of SF, choose * * * * * * * * */

/* * * * * * * CR choose * * * * * * * * */
//CR=1;////the Error coding rate=4/5
CR=2;////the Error coding rate=4/6
//CR=3;////the Error coding rate=4/7
//CR=4;////the Error coding rate=4/8
/* * * * * * * end of CR choose * * * * * * * * */
break;

Case 2:
/BW choose * * * * * * * * * * * * */
//gb_BW=1;/BW/10.4 K
//gb_BW=2;/BW/15.6 K
//gb_BW=3;/BW/20.8 K
//gb_BW=4;/BW/31.2 K
//gb_BW=5;/BW/41.7 K
Gb_BW=6;/BW/62.5 K
//gb_BW=7;//125 KHZ BW
/* * * * end of BW choose * * * * * * * * */

//gb_SF=0;//SF=6; 64 chips/symbol
//gb_SF=1;//SF=7; 128 chips/symbol
//gb_SF=2;//SF=8; 256 chips/symbol
//gb_SF=3;//SF=9; 9 512 chips/symbol
//gb_SF=4;////SF=10; 1024 chips/symbol
Gb_SF=5;////SF=11; 2048 chips/symbol
//gb_SF=6;//SF=12; 4096 chips/symbol

/* * * * * * * CR choose * * * * * * * * */
//CR=1;////the Error coding rate=4/5
CR=2;////the Error coding rate=4/6
//CR=3;////the Error coding rate=4/7
//CR=4;////the Error coding rate=4/8
/* * * * * * * end of CR choose * * * * * * * * */
break;

Case 4://125 KHZ BW SF=10; The Error coding rate=4/6
/BW choose * * * * * * * * * * * * */
//gb_BW=1;/BW/10.4 K
//gb_BW=2;/BW/15.6 K
//gb_BW=3;/BW/20.8 K
//gb_BW=4;/BW/31.2 K
//gb_BW=5;/BW/41.7 K
//gb_BW=6;/BW/62.5 K
Gb_BW=7.//125 KHZ BW
/* * * * end of BW choose * * * * * * * * */

/* * * * * * * SF, choose * * * * * * * * */
//gb_SF=0;//SF=6; 64 chips/symbol
//gb_SF=1;//SF=7; 128 chips/symbol
//gb_SF=2;//SF=8; 256 chips/symbol
//gb_SF=3;//SF=9; 9 512 chips/symbol
Gb_SF=4;////SF=10; 1024 chips/symbol
//gb_SF=5;////SF=11; 2048 chips/symbol
//gb_SF=6;//SF=12; 4096 chips/symbol
/* * * * end of SF, choose * * * * * * * * */

/* * * * * * * CR choose * * * * * * * * */
//CR=1;////the Error coding rate=4/5
CR=2;////the Error coding rate=4/6
//CR=3;////the Error coding rate=4/7
//CR=4;////the Error coding rate=4/8
/* * * * * * * end of CR choose * * * * * * * * */
break;
Case 8:
//FSK
break;
Default://10.4 SF, K=7; Cr=4/6
/BW choose * * * * * * * * * * * * */
Gb_BW=1;/BW/10.4 K
//gb_BW=2;/BW/15.6 K
//gb_BW=3; nullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnull
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