Lab report
1. Design principle of
Barker code correlator can detect peak barker code sequence, and in the case of 1 bits error detection peak barker code sequence,
Barker code is in the early 1950 s r.h. buck put forward a kind of binary code group with special regularity, it is a non-periodic sequence, a n a barker code (x1, x3,... Xn), each element is only possible value + 1 or - 1, and the eleven barker code is 11 'b11100010010,
2. Design
Barker code detector input is a sequence, need to move to the shift register first, then the values in the shift register with standard barker code or, by whether with or value is greater than the threshold value to determine the barker code,
Barker code detector structure diagram is as follows:


Module design:


3. The program code
The module buc (CLK, RST, din, valid, threshold).
The input CLK.
Input RST.
Input din;
Input (3-0) threshold;
The output valid;
Wire [10:0] data_buc;
Wire [3-0] threshold;
//reg valid???

Buc_devider U1 (din_buc (data_buc), the threshold (threshold), the valid (valid));
Buc_receiver U2 (CLK (CLK), the RST (RST), the din (din), the dout_buc (data_buc));
Endmodule

The module buc_receiver (CLK, RST, din, dout_buc);
The input CLK.
Input RST.
Input din;
The output/10:0 dout_buc;
Reg [10:0] dout_buc;

Always @ (posedge CLK or negedge RST)
if(! RST)
The begin
Dout_buc & lt; B0=11 ';
End
The else
The begin
Dout_buc={dout_buc [9:0], din};
End
Endmodule

The module buc_devider (din_buc, threshold, valid);
Input [10:0] din_buc;
Input (3-0) threshold;
The output valid;
Reg valid;
Reg [Wednesday] sum;
Integer (I);
The parameter BUC=11 'b11100010010;

Always @ (din_buc)
The begin
Sum=0;
for(i=0; i<12. I=I + 1)
If (din_buc ^ ~ BUC [I] [I]==1)
Sum=sum + 1;
The else
Sum=sum - 1;
End
Always @ (sum or threshold)
The begin
If (sum [4]==0)
The begin
If (sum (3-0) & gt;=threshold)
Valid=1;
The else
Valid=0;

End
The else
Valid=0;
End
Endmodule


//` timescale ns/1 ns;
The module buc_tb;
Reg the CLK.
Reg RST.
Reg din;
Reg [3-0] threshold;
Reg [32:0] data;

Initial
The begin
CLK=1 'b0;
Forever
# 10 CLK=~ CLK;
End

Initial
The begin
RST=1 'b0;
# 5 RST=1 'b1;
End

Initial
The begin
data=https://bbs.csdn.net/topics/33 'b111000100111110001000111100010010;
Threshold=4 'b1001;
End

Integer (I);
Always @ (posedge CLK or negedge RST)
if(! RST)
The begin
Din=1 'b0;
I=32;
End
The else
The begin
If (I==0)
The begin
Din=data [I];
I=32;
End
The else
The begin
Din=data [I];
I=I - 1;
End
End

Buc v1 (CLK (CLK), the RST (RST), din (din), the valid (valid), the threshold (threshold));

Endmodule
4. The simulation test


5. Circuit analysis
According to the simulation of the output waveform graph:
1) first when RST=1 to din signal for asynchronous reset operation
(2) when the CLK rose along the arrival, the data [32]=1 is assigned to din, data_buc for 00000000001 at this moment, at this time buc_divider detector sum=- 11 _1011 (1), does not meet the sum>=9, valid output is 0, meaning that did not detect the 11 barker code, at the moment I=31
(3) when the input is detected barker code, valid=1; I=32, tested again