Always @ (posedge CLK or negedge RSTZ)
The begin
if(! RSTZ)
The begin
The count & lt;=3 'b0;
W & lt;=1 'b0;
End
The else
If (en==1 'b1)
The begin
If (count==3 'd4)
The begin
The count & lt;=3 'b0;
W & lt;=1 'b1;
End
The else
The begin
The count & lt;=count + 3 'b1;
W & lt;=1 'b0;
End
End
The else
The begin
The count & lt;=count + 3 'b1;
W & lt;=1 'b0;
End
End
The else
The begin
The count & lt;=3 'b0;
W & lt;=1 'b0;
End
End
CLK rise along the arrival, en from 1 to 0, the if (en==1 'b1) was set up?

CodePudding user response:

Established, CLK rise along the arrival en change, if before the judgment is en change value

CodePudding user response:

When writing the temporal logic, it is suggested that in the non - blocking assignment with a delay, such as the w & lt;=1 'b0; Written w & lt;=# 1 1 'b0;

Behavior, and this delay is to simulate the actual circuit in the CLK rise after a period of time, on the Q of DFF can see changes brought on by a D,

It also avoids the RTL simulation when you said en in CLK rose along the change, judging if the en with 0 or 1 (because your en should also by other DFF Q after combination logic operations, will be along with the clock a stagger)

Is your writing now, generally speaking is like the above said if judgment is en changes the value of the former, but and en are written assignment (blocking/non - blocking), or even different EDA Tool in simulation processing way may be different,