CodePudding user response:
Process is repeated send auto reply and should have been blocked,,#include
#include
Typedef unsigned char uchar;
Typedef unsigned char uint;
//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * NRF24L01 port definitions are * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Sbit MISO=P1 ^ 4;
Sbit MOSI=P1 ^ 5;
Sbit SCK=P1 ^ 7;
Sbit CE P1=^ 0;
Sbit CSN P1=^ 1;
Sbit IRQ P1=^ 3;
//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * bee apparatus for * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Sbit BELL=P3 ^ 5;
//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * NRF24L01 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
# define TX_ADR_WIDTH 5//5 uints TX address width
# define RX_ADR_WIDTH 5//5 uints RX address width
# define TX_PLOAD_WIDTH 20//20 uints TX content
# define RX_PLOAD_WIDTH 20//20 uints TX content
X34 uint const TX_ADDRESS [TX_ADR_WIDTH]={0, 0 x43, 0 x10, 0 x10, 0 x01};//local address
X34 uint const RX_ADDRESS [RX_ADR_WIDTH]={0, 0 x43, 0 x10, 0 x10, 0 x01};//receiving address
//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * NRF24L01 register instruction * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
# define READ_REG 0 x00//read instruction register
# define WRITE_REG 0 x20//write instruction register
# define RD_RX_PLOAD 0 x61//receives the data read instructions
# define WR_TX_PLOAD 0 xa0//write instruction pipeline data
# define FLUSH_TX 0 xe1//wash send FIFO order
# define FLUSH_RX 0 xe2//flush receive FIFO instructions
# define REUSE_TX_PL 0 xe3//define repetitive loading data instructions
# define the NOP 0 XFF//keep
//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * SPI (nRF24L01) register address * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
# define CONFIG 0 x00//configured to send and receive state, CRC check pattern and the way the transceiver status response
# define EN_AA 0 x01//automatic reply function set
# define EN_RXADDR 0 x02//available channel setting
# define SETUP_AW 0 x03//transceiver address width
# define SETUP_RETR 0 x04//automatic retransmission function set
# define RF_CH 0 x05//working frequency setting
# define RF_SETUP 0 x06//emission rate, power consumption feature set
# define STATUS 0 x07//STATUS register
# define OBSERVE_TX 0 x08//send the monitoring function
# define 0 x09/CD/address detection
Channel # define RX_ADDR_P0 x0a//0 0 receives the data address
# define RX_ADDR_P1 0 x0b//channel 1 to receive data address
# define RX_ADDR_P2 0 x0c//channel 2 receive data address
# define RX_ADDR_P3 0 x0d//channel 3 receive data address
# define RX_ADDR_P4 0 x0e//channel 4 receive data address
# define RX_ADDR_P5 0 x0f//channel 5 receiving data address
# define TX_ADDR 0 x10//sending address register
# define RX_PW_P0 0 x11//receiving channel 0 receives data length
# define RX_PW_P1 0 x12//receiving channel 0 receives data length
# define RX_PW_P2 0 x13//receiving channel 0 receives data length
# define RX_PW_P3 0 x14//receiving channel 0 receives data length
# define RX_PW_P4 0 x15//receiving channel 0 receives data length
# define RX_PW_P5 0 x16//receiving channel 0 receives data length
# define FIFO_STATUS 0 x17//FIFO into the stack out status register Settings
//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Void Delay (unsigned int s);
Void inerDelay_us (unsigned char n);
Void init_NRF24L01 (void);
Uint SPI_RW (uint uchar);
Uchar SPI_Read (uchar reg);
Uint SPI_RW_Reg (uchar reg, uchar value);
Uint SPI_Read_Buf (uchar reg, uchar * pbufs, uchar uchars);
Uint SPI_Write_Buf (uchar reg, uchar * pbufs, uchar uchars);
Void nRF24L01_TxPacket (unsigned char * tx_buf);
//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * long time delay * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Void Delay (unsigned int s)
{
unsigned int i;
for(i=0; i
//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Uint bdata sta.//status flag
Sbit RX_DR=sta ^ 6;
Sbit TX_DS=sta ^ 5;
Sbit MAX_RT=sta ^ 4;
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
/* delay function
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Void inerDelay_us (unsigned char n)
{
For (; N> 0; N -)
_nop_();
}
//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
/* NRF24L01 initialization
//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Void init_NRF24L01 (void)
{
InerDelay_us (100);
CE=0;//chip enable
CSN=1;//Spi disable
SCK=0;//
IRQ=1;
SPI_Write_Buf (WRITE_REG + TX_ADDR TX_ADDRESS, TX_ADR_WIDTH);//write local address
SPI_Write_Buf (WRITE_REG + RX_ADDR_P0 RX_ADDRESS, RX_ADR_WIDTH);//write the receiver address
SPI_RW_Reg (WRITE_REG + EN_AA, 0 x00);//channel 0 automatic ACK response allows
SPI_RW_Reg (WRITE_REG + EN_RXADDR, 0 x01);//only channel allows the receiving address 0, if you need more channels can be reference Page21
SPI_RW_Reg (WRITE_REG + SETUP_RETR, 0 x00);//500 us + 86 us, 10 retrans...
SPI_RW_Reg (WRITE_REG + RF_CH, 0);//set the channel work 2.4 GHZ, sending and receiving must agree
SPI_RW_Reg (WRITE_REG + RX_PW_P0 RX_PLOAD_WIDTH);//set to accept data length
SPI_RW_Reg (x07 WRITE_REG + RF_SETUP, 0); nullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnull