For big mistake: what Warning (10230) : Verilog HDL the assignment Warning at Count_4bit. V (44) : truncated value with the size 32 to match the size of the target (4)
Error (10028) : Can 't resolve multiple constant drivers for.net "Q [3]" at Count_4bit. V (28)
Error (10029) : Constant driver at Count_4bit. V (7)
Error (10028) : Can 't resolve multiple constant drivers for.net "Q [2]" at Count_4bit. V (28)
Error (10028) : Can 't resolve multiple constant drivers for.net "Q [1]" at Count_4bit. V (28)
Error (10028) : Can 't resolve multiple constant drivers for.net "Q [0]" at Count_4bit. V (28)
Error (10028) : Can 't resolve multiple constant drivers for.net "Cy" at Count_4bit. V (28)
Error (12153) : Can 't elaborate top - level user hierarchy
Info (144001) : Generated suppressed the messages file D:/exp4_count output_files/Count_4bit map. SMSG
Error: the Quartus II 64 - Bit Analysis & amp; Short was unsuccessful. 7 errors, 2 warnings
Error: Peak virtual memory: 4585 megabytes
Error: Processing ended: Mon Nov 4 22:23:58 2019
Error: the Elapsed time: 00:00:01
Error: the Total CPU time (on all processors) : 00:00:00
Error (293001) : the Quartus II Full Compilation was unsuccessful. 2 warnings and errors,


The module Count_4bit (CLK, EN, Q, nCR, Cy, a, b, c, d, e, f, g, h);
The input CLK, EN, nCR;
The output (3-0) Q;
The output Cy, a, b, c, d, e, f, g, h;
Reg (3-0) Q;
Reg Cy, a, b, c, d, e, f, g, h;
Always @ (posedge CLK)
The begin
If (nCR) ~
The begin
Q<=0;
Cy<=0;
End
Else if (EN)
The begin
If (Q==49999999)
The begin
Q<=0;
Cy=1;
End
The else
The begin
Q<=Q + 1;
Cy=0;
End
End
End
Always @ (posedge CLK)
The begin
If (nCR) ~
The begin
Q<=0;
Cy<=0;
End
Else if (EN)
The begin
If (Q==9)
The begin
Q<=0;
Cy=1;
End
The else
The begin
Q<=Q + 1;
Cy=0;
End
End
End
Always @ ({Q})
The begin
Case ({Q})
4 'd0: {h, g, f, e, d, c, b, b}=8' b1100_0000;
4 'd1: {h, g, f, e, d, c, b, b}=8' b1111_1001;
4 'd2: {h, g, f, e, d, c, b, b}=8' b1010_0100;
4 'd3: {h, g, f, e, d, c, b, b}=8' b1011_0000;
4 'd4: {h, g, f, e, d, c, b, b}=8' b1001_1001;
4 'd5: {h, g, f, e, d, c, b, b}=8' b1001_0010;
4 'd6: {h, g, f, e, d, c, b, b}=8' b1000_0010;
4 'd7: {h, g, f, e, d, c, b, b}=8' b1111_1000;
4 'd8: {h, g, f, e, d, c, b, b}=8' b1000_0000;
4 'd9: {h, g, f, e, d, c, b, b}=8' b1001_0000;
Default: {h, g, f, e, d, c, b, b}=8 'b1111_1111;
Endcase
End
endmodule