Home > other >  Help: verilog drive digital tube light in turn
Help: verilog drive digital tube light in turn

Time:10-30

The module aa0106 (CLK, en, Q, codeout);
The input CLK, en;
The output [beat] codeout;
The output reg (2-0) Q;
Bb0106 bb0106 (outcode, Q);
Cc0106 cc0106 (CLK, en, Q);
Endmodule

The module bb0106 (CLK, en, Q);
The input CLK, en;
The output reg (2-0) Q;
Always @ (posedge CLK)
The begin
If (en==1 'b1)
The begin
If (Q & lt; 3 'd5)
Q & lt;=Q + 1 'b1;
The else
Q & lt;=0;
End
The else
Q & lt;=Q;
End
Endmodule

The module cc0106 (codeout, Q);
Input (2-0) Q;
The output [beat] codeout;
Reg [beat] codeout;
Always @ (Q)
The begin
Case (Q)
=6 '3' d0: codeout b011111;
D1: codeout=3 '6' b101111;
D2: codeout=3 '6' b110111;
=6 '3' d3: codeout b111011;
=6 '3' d4: codeout b111101;
=6 '3' d5: codeout b111110;
Default: codeout=6 'bx;
Endcase
End
Endmodule
Is the code I wrote above, the periphery of the counter is used to implement the digital tube light in turn, I was total Yang digital tube, but found that after download input can make en can light up a, not loop, I think it's grammar problems, seek help from your bosses, experimental tonight

CodePudding user response:

Is it because a case statement did not use non-blocking

CodePudding user response:

Try to reduce the CLK frequency

CodePudding user response:

Always @ (Q) with the CLK frequency doubling the place to try

CodePudding user response:

Each digital tube has an enabling signal, how you can use a en to control all digital tube? And your caller's input and output have problem
  • Related