Home > other >  For help! A little about VHDL design
For help! A little about VHDL design

Time:10-30

Have no great god can give some relevant program code, or provide a little thinking,

CodePudding user response:

Is counting with different initial value, to create different high and low level signals

CodePudding user response:

A counter, as the output signal is the highest
  • Related