Modeled after buying the FPGA development board schematic diagram, PCB, his paintings plate welding, chip is ALTERA EP1C3T100C8N, download debugging, software QUARTUSII progress bar shows that 100% above, but the program did not downloaded to the board, AS in curing a program can be completed, and then use the JTAG can download properly, welding for three board, is the problem, consult predecessors how did this happen? This is where setting problem? If the JTAG circuit is wrong, should not can download is all the time,

CodePudding user response:

Curing only one will run on electricity, then use the jtag links should be initialized, reset the signal isn't it