Use haisi SPI data transmission, 24 mspi clock, found that after every two byte, the waiting time would become, CLK was down more than 1 us directly, at the time of 12 m without this phenomenon, cause the overall transfer rate, so any increase the 24 m is no more than 12 m, and even lower, CLK was 12 m when transmitted waveform, above as the CLK, the following for the output, the output for all F, can see the basic fixed interval between each byte CLK was 12 m when transmitted waveform, above as the CLK, the following for the output, the output for all F, you can see every two bytes, CLK stopped have more than 1 us
CodePudding user response:
Post a slip of the pen, zhang is 24 m 2 SPI CLK time waveform figure
CodePudding user response:
The building Lord, solved? Here I use hi3531a to FPGA hardware spi communication, Set speed=20 * 1000 * 100, the results of the oscilloscope measurement is 31.2 MHZ (right) Set speed=10 * 1000 * 100, the results of oscilloscope measurement is 10 MHZ (right)
CodePudding user response:
After reading the data processing time, both 12 m and 24 m should be the same (CPU frequency constant),
CodePudding user response:
The building Lord, you still there? I want to ask SPI sent to from the machine, how to use the DMA way
