Output 110 m 90 m reference clock, need intermediate frequency, USES eight times interpolation, reg1 configuration, 11001000, 01111101 reg8 configuration, reg9 configuration 10110010, reg10 configuration 11100000. The reference clock to use the differential signal, common mode voltage of 400 mv, vpp900mv, chip has been unable to lock, which have a great god used internal phase-locked loop, strives for the answer,