Four data register: EAX, EBX, ECX, EDX
2 indexing and pointer register ESI and EDI
Two pointer register ESP and EBP
Six segment registers ES, CS, SS, DS, the FS and GS
1 the instruction pointer register EIP
A sign register EFlags
1, the data register (EAX EBX ECX EDX)
Data register is mainly used to store information such as operands and computing results, thereby saving read operands required to take bus and access memory time,
32 bit CPU has four 32-bit general-purpose registers EAX and EBX, ECX and EDX, the low 16 bits of data access, does not affect the high 16 bits of data, the
Low 16-bit registers respectively named: AX, BX, CX, DX
4 a 16-bit registers can be divided into eight separate 8-bit registers (AX: AH - AL, BX, BH - BL, CX: CH - CL, DX: DH - DL), each send
Store all have their own name, but independent access,
AX
Register AX and AL (Accumulator), commonly known as an Accumulator with Accumulator operation may need less time, Accumulator can be used to multiply,
In addition, the input/output operations, such as their use frequency is very high;
BX
Register BX, called the Base address Register (Base Register), it can be used as memory pointer;
CX
CX called Count registers (Count Register), the loop and string operations, we will use it to control cycles; In operating
, when move over, the CL to indicate the shift of digits;
DX
DX called Data registers (Data Register), in to multiply, divide, it can be used as the default operands to participate in the operation, also
Can be used to store the I/O port address,
In 16 bit CPU, AX, BX, CX and DX cannot serve as base and the index register to store the address of the storage unit, but can in 32 CPU,
2, the index register (ESI EDI)
32-bit cpus have two 32-bit general-purpose registers ESI and EDI, the low 16 bits corresponding previously CPU of SI and DI, the low 16 bits of data access, do not affect
High 16 bits of data,
Register ESI, EDI, called Index Register (the Index Register), they are mainly used for storing storage unit within the period of the offset, use them to achieve a variety of memory operand addressing mode, for different forms of address to access the storage unit to provide convenient,
Index register is divided into eight registers, as a general purpose registers, can be stored the operands and operations of arithmetic logic operation as a result,
,
3, the pointer register (EBP, ESP)
32-bit cpus have two 32-bit general-purpose registers EBP and ESP, the low 16 bits on previously BP and SP in the CPU, the low 16 bits of data access, does not affect the high 16 bits of data,
EBP register, ESP, called pointer register (PointerRegister), mainly used for the storage stack storage unit in the migration,
Pointer register is divided into
Eight registers, as a general purpose registers, can be stored the operands and operations of arithmetic logic operation as a result,
They are mainly used for access storage cells in the stack, and regulation:
BP based Pointer (Base Pointer) register, use it to directly access the stack
The data;
SP is the Stack Pointer (Stack Pointer) register, use it only accessible Stack,
4, the segment registers (CS, DS and ES, SS, FS, GS)
Segment register is set up according to the management mode of the memory section, the value of the physical address memory cells in the segment registers and a combination of an offset, so less available two digit value combined into a larger physical space can be accessed memory addresses,
Within the period of CPU registers:
CS - Code Segment registers (Code Segment Register)
"Jum segment address: offset"
Jmp ax, executes instructions before: ax=1000 h, IP cs=2000 h, 0003 h=
After executing instructions: ax=1000 h, IP cs=2000 h, 1000 h=
DS - Data Segment registers (Data Segment Register)
Mov ax, 1000 h
Mov ds, ax
ES - additional Segment registers (Extra Segment Register)
SS - Stack Segment registers (Stack Segment Register)
Mov ax, 1000 h
Mov ss, ax
Mov sp, 0010 h
FS - additional Segment registers (Extra Segment Register)
GS - additional Segment registers (Extra Segment Register)
5, the instruction pointer register (IP)
32-bit expanded instruction pointer to the 32-bit CPU, and the EIP, EIP the low 16 bits of the same as the previous the IP function of CPU,
Instruction Pointer EIP, IP (Instruction Pointer) next time will execute instructions are stored in the code segment of the offset, in has the prefetch directive function of the system, the next time to perform instructions are usually has been prefetching to queue, unless the shift happens, therefore, to understand their function, without considering the condition of the command queue, under the real way, because each segment of the maximum range of 64 k, therefore, high 16 must have 0 of the EIP, at this point, the equivalent of only the lower 16 IP to reflect in the program Instruction execution order,
