The module mem1x32 (outdata, indata writeEn, CLK, RST);

The output reg [31:0] outdata;//read port
Input [31:0] indata;
Input writeEn;
The input CLK.
Input RST.

Always @ (posedge CLK)
The begin
If (RST)
OutdataThe else
The begin
If (writeEn)
Outdata<=indata;
End
End
Endmodule

The module mux32_1 (outd in0, in1 and in2, in3, in4, in5, in6, in7, in8, in9,
In10 in11, in12, in13 in14, in15, in16, in17, in18, in19,
In20 in21, in22 in23, in24, in25, in26, in27, in28, in29,
In30 in31, addr);

The output reg [31:0] outd;
Input 31:0 in0, in1 and in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16,
In17 in18, in19 in20, in21, in22, in23, in24, in25, in26, in27, in28, in29, in30, in31;
Input [Wednesday] addr.

Always @ (addr)
The begin
Case (addr)
5 'd0: outd=in0;
5 'd1: outd=in1;
D2: outd=5 'in2.
5 'd3: outd=in3;
5 'd4: outd=in4;
5 'd5: outd=in5;
5 'd6: outd=in6;
5 'd7: outd=in7;
5 'd8: outd=in8;
5 'd9: outd=in9;
5 'd10: outd=in10;
5 'd11: outd=in11;
5 'd12: outd=in12;
5 'd13: outd=in13;
5 'd14: outd=in14;
5 'd15: outd=in15;
5 'd16: outd=in16;
5 'd17: outd=in17;
5 'd18: outd=in18;
5 'd19: outd=in19;
5 'd20: outd=in20;
5 'd21: outd=in21;
5 'd22: outd=in22;
5 'perhaps: outd=in23;
5 'd24: outd=in24;
5 'd25: outd=in25;
5 'd26: outd=in26;
5 'd27: outd=in27;
5 'd28: outd=in28;
5 'd29: outd=in29;
5 'd30: outd=in30;
5 'd31: outd=in31;
Default: outd=32 'dz;
Endcase
End
Endmodule



The module mem32x32 (readdata1, readdata2 readaddr1, readaddr2, writedata, writeaddr, writeEn, CLK, RST);

The output/31:0 readdata1;
The output/31:0 readdata2;
Input [Wednesday] readaddr1;
Input [Wednesday] readaddr2;
Input [31:0] writedata;
Input [Wednesday] writeaddr;
Input writeEn;
The input CLK.
Input RST.

Wire 31:0 m0, m1, m2, m3, m4, m5, m6 and m7, m8, m9, m10, m11, m12, m13, m14, m15, m16,
M17, m18 m19, m20, m21, m22, m23, m2-m24, m25, m26, m27, m28, m29, (, m31.

//decode 5 bit address to 32
Wire [31:0] en;
The assign en [0]=(~ writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [1]=(writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [2]=(~ writeaddr [0]) & amp; (writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [3]=(writeaddr [0]) & amp; (writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [4]=(~ writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [5]=(writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [6]=(writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [7]=(writeaddr [0]) & amp; (writeaddr [1]) & amp; (writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [8]=(~ writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [9]=(writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [10]=(~ writeaddr [0]) & amp; (writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [11]=(writeaddr [0]) & amp; (writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [12]=(~ writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (writeaddr [2]) & amp; (writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [13]=(writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (writeaddr [2]) & amp; (writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [14]=(~ writeaddr [0]) & amp; (writeaddr [1]) & amp; (writeaddr [2]) & amp; (writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [15]=(writeaddr [0]) & amp; (writeaddr [1]) & amp; (writeaddr [2]) & amp; (writeaddr [3]) & amp; (~ writeaddr [4]) & amp; WriteEn,
En [16]=(~ writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (writeaddr [4]) & amp; WriteEn,
En [17]=(writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (writeaddr [4]) & amp; WriteEn,
En [18]=(~ writeaddr [0]) & amp; (writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (writeaddr [4]) & amp; WriteEn,
En [19]=(writeaddr [0]) & amp; (writeaddr [1]) & amp; (~ writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (writeaddr [4]) & amp; WriteEn,
En [20]=(~ writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (writeaddr [4]) & amp; WriteEn,
En [21]=(writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (writeaddr [4]) & amp; WriteEn,
En [22]=(writeaddr [0]) & amp; (~ writeaddr [1]) & amp; (writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (writeaddr [4]) & amp; WriteEn,
En [23]=(writeaddr [0]) & amp; (writeaddr [1]) & amp; (writeaddr [2]) & amp; (~ writeaddr [3]) & amp; (writeaddr [4]) & amp; nullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnull