In 2013-07-03 he read: 4565
Basic operation
Here will briefly introduce the basic operation of NAND Flash in NAND Flash, how is the internal basic operations include: read, write and erase,
Read:
When we read the data from a storage unit (as shown in figure 2.4), is the use of a gate voltage Vread (0 v) on the gate side, and has not been read the gate end of the storage unit is partial in Vpass. R (usually 4 to 5 v), so that they can no matter how many and can pass transistor threshold voltage is, in fact, a been erased Flash memory cell with a lower than 0 v Vth value, and a storage unit was written a Vth tend to have a positive, and the size of the values generally lower than 4 v, in fact, the 0 v to a gate terminal of the selected memory cell bias, all together will go to the storage unit of the conduction current, and only by addressing the storage unit will be erased,
[NAND] NAND Flash basic operation, read, write, erase the X
List of current usually value in 100 - about 200 na, read the storage unit of charging technology is based on the integration, the parasitic capacitance of the use of bitline,
The capacitance is to use a fixed value (usually 1-1.2 V) for early charging: only when the storage unit is erased and current is released, then the capacitance only
Will be released, there are some circuit are specially used to detect the parasitic capacitance bitline state: in figure 2.4 shows this structure is the most current applications
Structure, bitline parasitic capacitance is marked Cbl, whereas NAND Flash string is equivalent to a current generator,
PMOS transistor in the charging process of bitline Mp was has been grounded, door and the door of the NMOS transistor Mn were kept in a fixed value V1. V1 of typical values will be about 2 v, there will be one at the end of the charging bitline voltage Vbl,
Vbl=V1 - Vthn (2.1)
In the formula above Vthn represents the threshold voltage of NMOS Mn,
In this time of Mn and Mp transistor is turned off, Cbl is free discharge, after a period of time (Tval), Mn gate will be offset in
V2 & lt; V1, usually at about 1.6 to 1.4 V,
If a Tval enough time of all complete discharge so bitline voltage:
Vbl=V2 - Vthn (2.2)
Mn will open and the output voltage (Vout) into a power-saving bitline, finally simulation voltage Vout will be converted into a digital value
Using a simple latch, about the read operation is certainly not so simple, more detailed, the subsequent we will continue to talk about
Write:
NAND Flash write operation is to use electronic quantum effects of the channel, the emergence of electronic tunnel is due to a strong electric field, in particular,
Write and erase all depend on the polarity of the electric field,
In the process of writing, through the oxidation layer on the number of electrons is the electric field of a function: in fact, the electric field, the greater the through the oxidation layer on the number of electrons is
More, therefore, in order to improve the ability of writing, one of the available high electric field (the corresponding is high voltage) is essential, it is also a NAND Flash
The main drawback of writing way, because the oxide layer is affected by the voltage and decline on the function,
And main advantage is that this kind of writing way each storage unit current is very low, this also is the Fowler Nordheim mechanism more
Suitable for multiple storage units parallel write reason and NAND page size required,
Used for writing algorithms for NAND Flash memory cell is called a "Program & amp; Verify "algorithm, Verify is used to check whether the
If storage unit has reached the limit of a distribution,
To wrap electronic trigger to enter by the oxide layer of floating gate, we require the following conditions (as shown in figure 2.5) :
Vdd is applied to drain select tapping
Vpass. P (8-10 v) ACTS on the door has not been asked for
Vpgm (20 to 25 v) ACTS on the choice of the door (a) that is about to be
GND effect in the source selection door
GND effect on to write the bitline
Applied to other bitline in Vdd
Self - boosting mechanism can prevent have the same gate to the storage unit of a write operation does not demand, so about this process a
The basic idea is in the process of writing using the storage unit of parasitic capacitance to develop his potential, of which is to increase in oxide tunnel
Under the potential of this area, (as shown in the figure below)
[NAND] NAND Flash basic operation, read, write, erase the
When the bitline is driven to Vdd, drain diode is a diode connected - tapping and corresponding bitline is floating, when Vpass. P
Be used to not selected to wordlines, parasitic capacitance can improve the potential of the channel, reduce the voltage drop through oxide channels, therefore,
This kind of phenomenon of channel should be banned,
Because of the storage unit architecture is matrix, all the storage unit of corresponding wordline is offset by the same voltage, even those not
Ready to be written of the storage unit is the same, they are called "disturbed", disturbs are two important symbol and write related: as shown in figure
2.5 Pass disturb and Program disturb will affect the stability of the storage unit,
Erase:
As shown in figure 2.6 a NAND memory is defined as a triple - well structure, usually every parts relate with his own triple - well,
While the source end is Shared by all of the block: use this method of matrix becomes more compact and structure can also be more diversity, the iP - well
Bias can also greatly reduce,
This kind of electron erased by using a high voltage and keep wordline grounding to offset the iP - well, in order to erase (such as
Figure 2.6 c), therefore, do not need negative voltage NAND technology, in addition, the physical mechanism is Fowler Nordheim - channel, because iP - well to
Some block is normal, so I can't in wordline floating cases have not choose to erase blocks, the
Methods when the iP - well is changed, due to the control gate and iP - well between capacitive double, floating wordline potential also improve the corresponding
The banned (Fowler Nordheim channel mechanism),
Figure 2.6 b probably draw the wipe at various stages of the algorithm and the specifications of the NAND to erase time requirement is very strict, therefore, the supply of NAND
Traders trying to go as far as possible steps complete erasure (best you just need to one step), as a result, in the process of erasing will have a very high electric field
Role to the matrix, and in fact be erased area is in the Vth value of negative migration, in order to make floating gate coupling the
Small, general will recommend after erase writing (PAE), the purpose is to able to erase the area to the limit value is close to 0 v,
(of course, also pledged not to exceed the limit value of read operation),
A SLC block erasure time is about 1-1.5 ms, and electronic erase pulse lasts about 700-800 us,
Process technical promotion and the decrease of the size of the complex algorithm more and degree of precision with higher requirements, especially for each storage unit 3/4 bit
Of this technique, in fact, the limit of reliability as technology improvements in reducing: more sophisticated and, of course, thus bring more problems, such as power consumption;
In order to be able to contain be erased the bandwidth of the area, now generally recommend PAE technology, in a nutshell, erasure time in the new NAND process technology will be
Add 4-5 ms,
About erasing algorithm behind will try to use a chapter to explain,
[NAND] NAND Flash basic operation, read, write, erase the
Logic structure:
NAND memory is a kind of unique way to store data, we can see from figure 2.7, a NAND is split up into multiple blocks and page
, a block is the smallest erase unit, any block contains more than one page, a block, the number of page is generally is a multiple of 16
(such as 64 or 128), a page is read and write the smallest addressable unit, each page is the primary area and leisure areas (see figure 2.8) is
The primary area size can be from 4 KB to 8 KB to 16 KB, and leisure area is be used for ECC, system pointer; Each of the 4 KB the primary area there are about hundreds of
Bytes of the free area,
[NAND] NAND Flash basic operation, read, write, erase the
Every time we want to carry out what operating a NAND, we must first trigger we want operation area of the address, the
Address is divided into rows and columns address, line said addressing the page address, listed address page said addressing specific byte, when row and column addresses all
When asked, the column address is given first, each address cycle is eight bits, ranks first cycle includes LSB, address addressing not
Can at the same time,
Line identify operations require block and address page, the page address is occupied the LSB.
[NAND] NAND Flash basic operation, read, write, erase the
Pinout:
NAND memory and external communication is to rely on pin (see figure 2.10), the pin is made by the Command Interface for measurement records,
The effect of the Command Interface is used to explain at some point to the operation of the NAND,
CE# : chip enable signal, enter "1" chips into the stand - by state, it is "0",
R/B# : Ready/Busy signal, the output signal is used to indicate the target state, when low said NAND operation is under way,
RE# : read enable signal, input signal used to enable the output of the data string,
CLE: command lock enabled, the input signal is used to represent the host end bus cycle is now used to input command,
ALE: address lock enabled, the input signal is used to represent the host end bus cycle is now used to enter the address,
WE# : write enabled, the input signal control lock/open for input data, data, command and address will rise in WE# along be locked,
WP# : write protected, the input signal is used to stop writing about NAND and erase operation,
DQ
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