Recent translation an assembler, use c8051f505 single-chip microcomputer, and the FPGA is address data bus communication, through the interrupt to read data in the address, assembler can run smoothly, I translated into found after assembly into the interrupt how also can not read the address data, strives for the great god, assembly code

 LJMP MAIN 
ORG 000 bh 
LJMP A1CDF 
ORG 001 bh 
LJMP A1CC8 


MAIN: 
ANL PCA0MD, # 0 BFH 


MOV SFRPAGE, # CONFIG_PAGE 
MOV OSCICN, c5h # 0 
MOV P0SKIP, # 3 h 
MOV P1SKIP, # 0 e0h 
MOV 0 # 00 h; Cross switch can make 
MOV XBR1, # 0 c0h 
MOV XBR2, # 040 h 
MOV P2MDIN, fh # 0; P0 port configuration, leakage, p1 and P4 port for push-pull output 
MOV P1MDOUT, # 0 e7h 
MOV P2MDOUT, # 0 fh 
MOV P3MDOUT FFH # 0; P0 - p4 port for the digital input, p2 four analog input port 
MOV P4MDOUT, # 0 FFH 
MOV EMI0CF, # 09 h 
MOV EMI0TC, # 045 h 
MOV SFRPAGE, # ACTIVE_PAGE; External storage Settings 

The CLR P1.1 
LCALL A1D30 
The CLR P1.0; 15530 master reset 
The CLR P1.4; Open to receive 
SETB EA. Clear the interrupt mask bit, open the CPU interrupt 
A1CC8: PUSH DPL; Son receives the interrupt service routine (T1 interruption) 
PUSH DPH 
PUSH the ACC 
MOV DPTR, # 02001 h 
MOVX A, @ DPTR 
JB b. 0, A1D19 
MOV RMSB, A 
MOV COM_DATA, # 00 h 
; SETB P2.1 
JNB P1.3, A1D1D 
MOV COM_DATA, # 0 FFH 
A1D1D: SETB b. 0 
SJMP LP5 
A1D19: MOV RLSB, A 
SETB b. 3 
SJMP LP5 

After translated into c

 void Oscillator_Init (void) 
{
SFRPAGE=CONFIG_PAGE; 
OSCICN=0 xc5; 
SFRPAGE=ACTIVE_PAGE; 

} 
Initialize the////timer A1D30 
Void Timer_Init (void) 
{
ET0=1; 
ET1=1; 
TR0=1; 
TR1=1; 
TMOD=0 x66; 
TL0=0 xf8; 
TH0=0 xf8; 
TL1=0 xf8; 
TH1=0 xf8; 
} 
Void EMI_IN (void) 
{
SFRPAG=CONFIG_PAGE; 
EMI0CF=0 x09;//configure EMIF port multiplexing method with block selection mode of fragmentation, & lt; 4 k of memory, & gt; 4 k with CRT 
EMI0TC=0 x45;//minimum address setup time, maximum holding time, the original value of 55 h 
SFRPAGE=ACTIVE_PAGE; 
} 
Void Port_IO_Init (void) 
{
SFRPAGE=CONFIG_PAGE; 
P0SKIP=0 x03;//the Skip P0.0 and P0.1 
P1SKIP=0 xe0-0xfc; 
XBR0=0 x00; 
XBR1=0 xc0;//T2 and T1, T0 connected to a port pin 
XBR2=0 x40;//can make cross switch 
P2MDIN=0 x0f;//set the P2 mouth no analog input 
P1MDOUT=0 xe7;//push-pull output load capacity 
P2MDOUT=0 x0f; 
P3MDOUT=0 XFF; 
P4MDOUT=0 XFF; 
SFRPAGE=ACTIVE_PAGE; 
} 
INTERRUPT (TIMER1_ISR INTERRUPT_TIMER1) 
{
If (BB0) 
{
X2001 RLSB=XBYTE [0]; 
BB3=1; 
} 

The else 
{
X2001 RMSB=XBYTE [0]; 
COM_DATA=https://bbs.csdn.net/topics/0x00; 
If (P13==0) BB0=1; 
The else 
{
COM_DATA=https://bbs.csdn.net/topics/0xff; 
BB0=1; 
} 
} 
} 

RMSB in c=XBYTE [0 x2001] this have what problem? Don't read the number

CodePudding user response:

Assembly is correct, C is not correct?

Ensure XBYTE [] is defined in the xdata area, and the starting address is correct, if the starting address is located at 0 x100 is your XBYTE [0 x2001] actually points to the xdata 0 x2101

For example xdata XBYTE [] __attribute__ ((section (". ARM __at_0x00 ")))

CodePudding user response:

Correction, the C51 should write
Xdata XBYTE [] _at_ 0 x00;

CodePudding user response:

Don't see the XBYTE [] definition, but RMSB=XBYTE [0 x2001] look, you sure that there is more than 0 x2001 c8051f505 microcontroller memory?

CodePudding user response:

reference 1st floor dceacho response:

is the assembly is correct, C is not correct?

Ensure XBYTE [] is defined in the xdata area, and the starting address is correct, if the starting address is located at 0 x100 is your XBYTE [0 x2001] actually points to the xdata 0 x2101

For example xdata XBYTE [] __attribute__ ((section (". ARM __at_0x00 ")))

I am directly add # include & lt; Absacc. H> The header file, the starting address? Through EMI0CF 3:2 set is 10, the instructions are as follows, the When EMI0CF (3:2) are set to 10, the XRAM memory map is split into two areas, on - chip space and off - chip space.
? The Effective addresses below the internal XRAM size boundary will access on - chip XRAM space.
? The Effective addresses above the internal XRAM size boundary will access off - chip space.
? 8-bit MOVX operations use the contents of EMI0CN to determine been the memory access is on - chip or off - chip. The upper 8 - bits of the Address Bus A [city] are determined by EMI0CN, and the lower
Eight bits of the Address Bus A [away] are determined by R0 or R1. All 16 - bits of the Address Bus A [15:0] are driven in "Bank the Select" mode.
? 16 - bit MOVX operations use the contents of DPTR to determine been the memory access is on - chip or off - chip, and the full 16 - bits of the Address Bus A [15:0] are driven during the off - chip transaction.
For more than 1000 pieces, no more than 1000 for on chip, 0000 to FFFF XRAM chart shows the ~ ~ ~

CodePudding user response:

reference worldy reply: 3/f

didn't see the XBYTE [] definition, but RMSB=XBYTE [0 x2001] look, you sure that there is more than 0 x2001 c8051f505 microcontroller memory?

I direct reference # include & lt; Absacc. H> Header files, and somebody else assembly has 2001 h, I don't know why I c language study, through EMI0CF 3:2 set is 10, the instructions are as follows, the When EMI0CF (3:2) are set to 10, the XRAM memory map is split into two areas, on - chip space and off - chip space.
? The Effective addresses below the internal XRAM size boundary will access on - chip XRAM space.
? The Effective addresses above the internal XRAM size boundary will access off - chip space.
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