Himself with the fpga nios setup, the system clock 144 m, sending and receiving cache controls are set to 8 k, but the use of TCP debugging assistant shows maximum rate only 40 to 50 KB, excuse me, you did what a place to need to pay attention, thank you first

CodePudding user response:

The original poster is what kind of hardware interface connected with W5500 USART, SPI, the FSMC, have to use the DMA, these are all available from hardware level, it is concluded that the rate at which a theory bottleneck