Use the ieee. Std_logic_1164. All;
Use the ieee. Std_logic_arith. All;
Use the ieee. Std_logic_unsigned. All;
The entity sipo is
The port (RST, din, CLK: in std_logic;
Dout: out std_logic_vector downto 0 (1));
End the sipo;
Architecture behav of sipo is
Signal q: std_logic_vector downto 0 (1);
The begin
The process (CLK, q, din, RST)
T: variable integer range 1 to 3;
The begin
If RST='1' then dout<="00";
Else if (t=3) then
T:=1;
Dout<=q;
Elsif (CLK 'event and CLK=' 1 ') then
T:=t + 1;
Q (0) & lt;=din;
Q (1) & lt;=q (0);
end if;
end if;
End the process.
End behav.
CodePudding user response:
T is post content?