The module part2 (CLK, rst_n, q);
The input CLK, rst_n;
The output reg [15:0] q;
Always @ (posedge CLK)
The begin
if(! Rst_n)
Q<=1 'b0;
The else
The begin
If (q==65535)
Q<=0;
The else
Q<=q + 1;
End
End
Endmodule
Look not to understand other people's code, the if (q==65535) here is what meaning, please guide

CodePudding user response:

A 16-bit binary full 1 equals 65535