50 MHZ clock control AD9238 collection 1 MHZ of function generator to generate sine wave, the wave before entering the AD in good condition, through the fpga: acquisition, fifo, wifi to send, after processing waveform appear obvious burrs, turn to the great god problem where

CodePudding user response:

Very regular blade, should be low sampling rate

CodePudding user response:

1 MHZ sine signal, with 50 MHZ AD sampling should be used

CodePudding user response:

May be you wrong data rearrangement, check the adc data conversion, string and multi-channel merger whether restore error in matlab, a simple method is to use an adc test mode, make the adc analog part of the disconnect, think you could reach the test sequence,

CodePudding user response:

Whether the data bits and AD pin definition is wrong, such as Bit0 and Bit1 replaced

CodePudding user response:

Check whether sawtooth frequency and amplitude corresponding to a certain place

CodePudding user response:

Only keep high see if, which have low bit has a problem