FPGA as the primary device to send data to the DSP of fixed address, send sent after the completion of the doorbell package, use a srio to IP core ireq_tready signal sent directly to come over, but now after this signal is sent to the two packages of data will have been down, also do not have yao luo female chu how this signal specific parse out, with bosses, whether to contact the could give directions

CodePudding user response:

A great god, and I also met you and the same question, do you solve this problem?

CodePudding user response:

Excuse me, would you please tell me how you solved the problem, I recently in the debug SRIO also encountered this problem, the DSP is on the other side of the issue or problem on this side of the FPGA ah, please give directions thank you

CodePudding user response:

reference 1st floor nunu0322 response:

great god, and I also met you and the same problem, would you solve this problem?

Is the problem that the FPGA, look tlast signal

CodePudding user response:

Excuse me, is what reason, I also have this problem

CodePudding user response:

This problem because without flow control, the number of fast, died, also can't restore,
Join the flow control or send several speed control can be solved,

CodePudding user response:

Hello! How would you like to join the flow control?

CodePudding user response:

refer to 7th floor Min0912 response:

hello! How would you like to join the flow control?

6th floor said is right, after sending a 256 - byte needs to wait for a few clock cycles, or in a large amount of data when they go wrong