Have bosses to help me have a look at, thank you very much:
I wrote a JK flip-flop appeared the mistake Error: Port "e" does not exist in primitive "nand3" of the instance "u0
"Really really don't know how to, hope have a big help
The LIBRARY IEEE.
USE the IEEE. STD_LOGIC_1164. ALL;
The ENTITY jk IS
The PORT (j, k, CLK: IN STD_LOGIC;
Q, nq: OUT STD_LOGIC);
END jk.
ARCHITECTURE struct OF jk IS
COMPONENT nand2
PORT (a, b: IN STD_LOGIC;
F: OUT STD_LOGIC);
END COMPONENT nand2;
COMPONENT nand3
PORT (in1 and in2 in3: IN STD_LOGIC;
E: out STD_LOGIC);
END COMPONENT.
SIGNAL x: STD_LOGIC_VECTOR (0 TO 3);
The BEGIN
U0: nand3 PORT MAP (k, CLK, x (3), x (0));
U1: nand3 PORT MAP (j, CLK, x (2), x (1));
U2: nand2 PORT MAP (x (0), x (3), x (2));
U3: nand2 PORT MAP (x (2), x (1), x (3));
Q<=x (3);
Nq<=x (2);
END struct;

The underlying file
The LIBRARY IEEE.
USE the IEEE. STD_LOGIC_1164. ALL;
The ENTITY nand3 IS
PORT (in1 and in2 in3: IN STD_LOGIC;
E: out STD_LOGIC);
END nand3;
ARCHITECTURE concerns OF nand3 IS
The BEGIN
E<=not (in1 and in2 and in3);
The END fitting concepts;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
The LIBRARY IEEE.
USE the IEEE. STD_LOGIC_1164. ALL;
The ENTITY nand2 IS
PORT (a, b: IN STD_LOGIC;
F: OUT STD_LOGIC);
END nand2;
ARCHITECTURE concerns OF nand2 IS
The BEGIN
f<=a nand b;
The END fitting concepts;

CodePudding user response:

VHDL is out the lowercase recognition is not very good

CodePudding user response:

This is not nand3 nand3, try renaming