One, application of power MOSFET, power loss will lead to produce hot, mainly by the loss of state, switch loss,. This is also the engineer, where applications mainly aimed at the optimization in this paper the leacom engineer/add Scilicon001 will according to the loss of all, to study the feasibility of reduce the power consumption of the every kind of solution,
Power loss is reduced, can from the hardware and software two aspects, this article talk about hardware level loss reduction plan, the first game leacom engineer/add Scilicon001 summary of the following eight parts of the loss (details will arrange article discussed separately - loss of power MOSFET) :
1, conduction power loss;
2, by the power loss;
3, open the process power loss;
4, the process of shut off power loss;
5, drive power loss;
6, Coss capacitor discharge loss;
7, parasitic diode to the are welding consumption: SC
8, parasitic diode reverse recovery MAO private
Two, the leacom engineer to discuss the feasibility plan
This section the leacom engineer/add Scilicon001 will in view of the above mentioned eight loss component, one by one to study the feasibility of hardware level to reduce the loss,
1, conduction power loss
Conduction in the whole power loss mainly comes from the power circuit resistance Rds (the heat generated in (on), review the calculation formula: Pon=IDSrms2 * Rds (on) * K * Don
From the formula, the drain current IDS and the premise of constant temperature coefficient K, reduce the loss of state way/only reduce state resistance Rds (on), and reduce the duty ratio,
Motor control, the duty ratio change impact torque output, this involves the control performance, need comprehensive consideration, this focus on the decrease of the resistance,
Loss of power MOSFET articles are mentioned, on state resistance Rds (on) influenced by temperature and carrier concentration, then you can from two aspects to reduce resistance:
A, optimize the design of the device itself and process;
B, optimize the external heat dissipation,
Compared to the VDMOS, Trench MOSFET has lower conduction resistance, larger current flows and faster switching speed, more widely used in low pressure areas,
On resistance is inversely proportional to the chip area, but increase the chip area to reduce the lead resistance, raises costs tend to be commercial products not allowed; And the introduction of minority carrier conductive, can reduce conduction voltage drop, but switch speed will be affected and the tail current, switching losses increase,
So on Rds (on) optimization, for hardware application engineer, sai leacom engineer/add Scilicon001 advice general optimization from the following two aspects: the selection of the design phase, the comprehensive consideration, choose as far as possible little Rds (on) the MOSFET; Pay attention to the design of radiator, completely conduction state, the Rds (on) as the positive temperature coefficient (will cause subsequent finishing series: power MOSFET losses of article five deadly SINS)
2, by the power loss
As loss from the loss caused by leakage current IDSS, first to understand how leakage current, according to the p-n junction of volt-ampere characteristic curve, when add reverse voltage, in the third quadrant, there was a period does not change with the voltage current () under the condition of constant temperature, which is the PN junction reverse saturation current, according to the above structure of MOSFET, leakage between source are two p-n junction, then inevitably has the reverse saturation current situation, also produce leakage current,
From the p-n junction of volt-ampere characteristic curve above knowable, within a certain range, the saturation voltage has nothing to do with the size of the leakage current, is related to temperature and so on by the power loss, can be in MOS selection stage, pay attention to the index of reverse saturation leakage current, on the other hand, the influence of temperature is larger, so the guarantee system in the state of downtime as, heat can out, almost able to ignore the loss,
3, the process of open power loss
Open process loss is caused by MOSFET open declining gradually in the process of drain-source voltage VDS and increasing source of leakage current IDS overlapping part of the energy loss caused by the
From the waveform to find ways to reduce the loss, that is, reducing the area of the junction Poff - on!
Applications can be optimized by means of the following:
1) adjusting the opening speed
To mention opening losses, opening speed can become everybody first adjust object, reduce the gate drive resistance, reduce the gate capacitance is the most direct and effective way, on the other hand, ensure driving voltage in the range of the rated the faster the speed, the higher the opened
Need to be aware of is too opened, will lead to the current rapid rise, as a result of the existence of stray inductance, can produce high voltage spike, which damage to the device, so you need to think comprehensively opened speed,
2) soft start circuit
Soft start circuit mainly stagger the peak voltage and current, current rise to higher value before the voltage value has been/is reduced to 0 v, through the adapter circuit, realize ZVS (zero voltage open), ZCS (zero current opening)
ZVS and ZCS for opening stage, need to pay attention to the following problems: the zero current opening:
Zero current open mainly using DCM mode, inductor current can't mutation, so as to realize the MOS opening drain the inductor current is zero, but zero current opening can't eliminate the drain charge loss, in CCM mode, the zero current opening must be done by auxiliary switch (at least two switch work together), zero voltage opened:
Zero voltage open mainly through auxiliary circuit will charge on Cds + Cgd implementation, thereby eliminating opening loss and drain charge loss,
"LLC resonant:
LLC resonant soft switch is the best practice of traditional soft switch, through collaboration between the switches, and adding auxiliary inductor and capacitor, reach the zero voltage switch of MOS, thus can basically eliminate switch loss and drain charge loss, but inevitably, the need to achieve zero voltage cut-off in leakage source in parallel between great capacity to absorb the shut off the current, which led to a huge amount of energy in/large current applications in the auxiliary of auxiliary capacitance and inductance network, due to the power load/light load and drain the storage charge is different, so in order to meet the resonance frequency of the fixed, PWM control device must work frequency,
4, the process of shut off power loss
Loss is shut off due to declining gradually in the process of mosfets off leakage source current IDS and the rising of the drain-source voltage VDS overlapping part of the energy loss caused by the
Sai leacom engineer/add Scilicon001 think like open process optimization methods, from the waveform to find out the ways to reduce the loss of shut oFF, and reduce the area of the junction PoN oFF! And waveform is similar, so the same optimization way, namely:
1) speed adjusting cut-off

2) soft shut off the circuitShut off speed adjustment with opening speed adjustment, mainly from the gate drive, optimizing the parameters and drive power supply, etc and ZVS and ZCS for shut off stage, "leacom engineer/add Scilicon001 remind need to pay attention to the following problems:
Zero voltage turn off
Zero voltage turn off the main is to use the capacitor voltage can't mutation characteristics, transferring the current on the MOS tube into Cds, thus ensuring the MOS current is zero Vds has remained a low value, reduce the loss of shut off, but it brings a problem, in the case of large current, is large enough for clamping Vds must ensure that the Cds and large Cds is actually shift off loss, to drain the charge loss,
Zero current turn off:
Usually MOS zero current turn off is not easy to the realization of intuitive, unless prior to MOS current transferred to other places (usually need auxiliary switch) together, in fact, zero voltage turn off will eventually achieve zero current turn off (MOS) in the current was transported to the Cds on the
If you use the auxiliary switch, the need to pay attention to the MOSFET misleading problem,
5, drive power loss
As shown in the picture on the right, for the common drive circuit circuit, driving loss, refers to the gate to accept drive power to drive caused by the loss,
Drive way, drive efficiency will exist difference/vision, under the condition of the same drive output power, caused by the loss, will also be different, the following formula is obtained the same device application, the maximum driving power loss:
PGS=VGS * Qg * fs
According to the formula for reduce the loss of the way, need in the design phase, focus on three variables:
1) the device Qg value;
2) driving voltage setting;
3) work frequency,
Leacom engineers/add Scilicon001 remind need to pay attention to, not to reduce loss, choose the parameters of the smaller, otherwise it will affect other system performance, such as driving voltage VGS this parameter, numerical small, as long as higher than the threshold voltage, the device can still conduction, but it may make the device work on half on state, on state at this time will be a big loss, affect the performance of the system, if the selection ', select Qg smaller devices, leads to the device is more likely to achieve open conditions, misleading increased risk,
In general drive loss is not too big, design need not deliberately reduce it and other performance, if must need optimization, driven/best idea is to promote efficiency, because of the totem pole drives, optical coupling isolation drive, transformer isolation drive efficiency is different, and thus drive loss (that is, the drive circuit fever) is different, different drive IC, different levels of design is different, also is it possible to optimize against the loss,
6, Coss capacitance discharge loss
Refers to the output capacitance Coss during MOSFET as storage of the electric field can, during the period of MOSFET conduction, in the discharge of the drain-source on loss,
The actual process, because of the influence of Coss, most of the current flows through MOSFET, through the Coss of very small, even negligible, thus Coss of charging is very slow, the rate of current rise VDS is very slow, namely:
Because of the existence of Coss, in the process of shut off, because the capacitor voltage can't mutation, so the voltage of the VDS has been to maintain in low voltage, power loss is small,
Because of the existence of the Coss, in the process of opening, capacitor voltage can't mutation, so the voltage of the VDS has been maintained at a higher voltage, real power loss is very big,
Coss discharge loss calculating formula for:
PDS VDS2Coss=1/2 * * fs
Coss loss mainly in the opening stage of the discharge and the capacitance value, frequency is proportional to, and is proportional to the square of the voltage, the power MOSFET data table, Coss corresponding to the power consumption is Eoss,
The direction of the application of design optimization is mainly from the Coss capacitance of the Cds by the leakage source capacitance and gate leakage of Cgd, but usually it is difficult to optimize the Cgd, because it often when modules or single pipe forming has been set up straight, and also with the Cgs Ciss input capacitance, the change will affect the miller platform,
So Cds do optimization, mainly for according to actual test results, choose appropriate Cds in parallel capacitor, neither to excessive absorption peak and parallel Cds, because of its stored energy release large amount of/in the opening phase, has led to an increased loss, even result in resonance, affects normal performance, also can't in order to reduce loss/want to consume, and too less capacitance, or voltage spike will be A headache, need according to the practical application environment to find the optimal value,
7, the loss of parasitic diode to the is
Parasitic diode to the is loss can not be ignored, especially in the large current application environment, the loss must be strictly controls the,
The loss occurs mainly during the power component of afterflow,, as shown in the picture on the right,
Computation formula is as follows:
Pd_f=IF "VDF * t3 * fs
IF for the diode forward current, VDF for diode to the positive pressure drop, t3 for diode forward stream of time,
From the application level, the optimization of main from VDF loss, selection in the design phase, the choice of VDF low device,
In addition to external structures, circuit, that is, do not use the module parasitic diodes stream, the external circuit, the use of external diode stream, make postproduction phase produces the loss doesn't stack to the power of the device, so as to improve device performance, as shown in the circuit, but it is important to note that as a result of the existence of D2, will increase the conduction losses, although the increase of loss are not superimposed on the MOSFET, but the efficiency of the whole system will be reduced, and D1, D2 selection and heat treatment will be annoying, recommended only in some application scenarios using this circuit,
8, parasitic diode reverse recovery loss ve
Reverse recovery is positive to the p-n junction of storage charge depletion, process back into off state, loss of energy is needed to complete the process of composition, ->
Shown in right to reverse the direction of the current in the recovery phase current of power devices, Irss is the reverse recovery current, the current through the bridge under this phase reverse recovery current for the inductor current and the bridge, the sum to the current waveform under the bridge, is the bridge to open place, there is a peak current, its size affected by opening speed, here is the main optimization of Irss becomes zero before the loss caused by the
Reverse recovery process it is important to have a parameter: the TRR (reverse recovery time), the impact of power MOSFET aso,
Reverse recovery time is too long, will lead to reverse recovery loss increase, more serious is the influence of affect the working frequency, because time is too long, lead to the death of the reserved area must be bigger, to ensure safety,
Reverse recovery time is too short, the rated flow, di/dt will be great, because style, will lead to a high peak reverse recovery phase, and damage to the device,
In view of the reverse recovery phase of the loss, the leacom engineer/add Scilicon001 Suggestions can from the following three aspects to optimize:
1) the switching speed of control right to control the reverse recovery time and make the device work to reduce the loss in safe area; 2) optimizing wiring at the same time, reduce the style, can have a great effect for losses,
nullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnull