STM32F429, the use of the FMC parallel bus operation, only a single chip microcomputer is the host address bus, hung up the memory, the other a few peripherals, such as the fpga from machine, on the bus after the 5.1 K resistor, when reading and writing control after the market-place, hope the address bus for the level to maintain state, or released into a high impedance state into a high level on (5.1 K), is that ok? Code should be how to set? But, thank you!
CodePudding user response:
Choose a invalid piece, address line does not affect you, didn't understand what are you going to do
CodePudding user response:
STM32 CPU FMC address/data bus, after the initial activation (FMC address data control pin initialization complete), address line and data line basically have no way to control their state, as long as you access the FMC bus, the state of the bus will be change, Some extreme operation can achieve what you want, such as initialization activated when accessing the FMC FMC this bus related pin, do not access the FMC then insert the pin you want to initialize the signal state, (does not recommend the style the way very much, there will be a lot of disadvantages) On hardware design, FMC CPU bus after a 162245 bus isolation driver, through some logic also can realize your intentions,
