(chapter 6 original memory hierarchy 6.1.1 third last paragraph) : circuit designers to DRAM organization into two-dimensional array rather than a linear array one reason is to reduce the number of chip address pins, for example, if the sample is organized into a 128 - bit DRAM 16 unit of linear array, address 0 ~ 15, then the chip will need 4 address pins rather than 2 ,

Here is not very understanding, two-dimensional array need two this easy to understand, but why is four linear array? Please have greatly help

CodePudding user response:

DRAM access to data, using the address transfer twice, the first row address, the second column transfer address

128 - bit, design of 8 bit to 16 units, linear array is 16 unit, need four address bits, but USES the two-dimensional array, is 4 x4, a 4 only need two address, transfer twice, you can query to the space of 4 x4

CodePudding user response:

Address reuse, reduce the external tube feet,

CodePudding user response:

Using two-dimensional way, address of each unit has two rows and columns, rows and columns are two addressing, example is the address of rows and columns in the 0 ~ 3, so I need 2 bits, said two pins,

 
00.00 00.01 00.02 00.03 
01.00 01.01 01.02 01.03 
02.00 02.01 02.02 02.03 
03.00 03.01 03.02 03.03 

Using linear address, address code is 0 ~ 15, need 4 bits, so need 4 pins,

 
00 06 07, 08 09 01 02, 03 04 05 0 0 0 0 0 b c d e 0 f 

CodePudding user response:

If it is two address can be achieved,

CodePudding user response:

Thank you thank you, to understand it

CodePudding user response:

I understand because each pin can only carry a signal, if the organization into a linear array, so in order to make the combination of the pin to cover this 16 address, because the fourth power of 2 is 16 just covering 16 address, so I need 4 pins,
And if the organization into a two-dimensional array, can be a 4 x4, each row and each column only 4 address, only covers two is enough,