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The powerful unknown about VHDL language & # x27; X & # x27; The simulation waveform of

Time:11-29

Himself wrote a R - S trigger code, then the behavior simulation, finally found that R=0, S=0, should be the q, qb is supposed to be disabled, I will give the signal is' X ', but in the end it has been a high level, oneself still in the preliminary stage, didn't understand the 'X', when the output signal should be 'X is, waveform figure should be high level or low level or random uncertainty, attached in your own code and simulation figure, thank you for the answer of,

The simulation diagram:


Code:
 
The library ieee.
Use the ieee. Std_logic_1164. All;

The entity r_s is
The port (r, s, cp: in std_logic;
Q, qb: out std_logic);
End r_s;

Architecture behav of r_s is
Signal rs: std_logic_vector downto 0 (1);
Signal q_s qb_s: std_logic;
The begin
Rs<=s& R;
The process (rs, cp)
The begin
If the cp 'event and cp=' 1 'then
If the rs="11" then q_s & lt;=q_s; Qb_s & lt;=qb_s;
Elsif rs="01" then q_s & lt;=not q_s; Qb_s & lt;='1'.
Elsif rs="10" then q_s & lt;=not q_s; Qb_s & lt;='0'.
Elsif rs="00" then q_s & lt;=not q_s; Qb_s & lt;='X';
End the if;
End the if;
End the process.
Q<=q_s; Qb<=qb_s;
End behav.


Thank you, HHH ~

CodePudding user response:

X is the uncertainty... You this is a software problem

CodePudding user response:

reference 1st floor Hwa_Zz response:
x is uncertainty... You this is a software problem
x is uncertainty, that is to say he is the high and low level of random or said at a specific value would turn a certain level or simulation has been the high level or low level
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