Doing composition principles of curriculum design, have not learned Verilog, code https://blog.csdn.net/linwh8/article/details/71308282 with reference to the blogger, but merely some simulation is not linear, strives for the big help, guidance,

Using modelsim, steps: building engineering, create. V file, compiled, and then start the simulation, do not know the steps to have error,

CodePudding user response:

No simulation diagram can only guess, first of all, look have set the clock simulation in the test file, and set the initial value, then see incentives have to write, finally see really if you have any questions, wiring connection bits wide if you have any questions, let's take a look at this a few, if the code is no problem to find the problem of test files