Problem description: use an LVDS RX IP core to receive data, for example, an LVDS clock is 250 MHZ, is dual channel AD data receiving,
The form of data, given a trigger, trigger, to write LVDSRX receives the signal into the FIFO, used for subsequent processing, trigger is in strict accordance with the 1 KHZ, data is similar to 1 after the trigger signal us there is a pulse signal, the signal is arguably is triggered strict fixed time to come, but found that LVDSRX receives the pulse signal there will always be a few random jitter clock inside, not strict fixed in one place, want to ask if this is LVDSRX receiving time will appear this problem, is that with what method can solve! Thank you for your attention!