Q: what is the difference between synchronous and asynchronous circuit?
Synchronous circuit, storage circuit in all of the clock input triggers the same clock source, and therefore all the status change of the trigger and the synchronous clock pulse signal,
Asynchronous circuit, clock circuit is not regulated, and some of the flip-flop is the input terminal connected to the clock pulse source, this is the trigger condition change and clock synchronization, while the rest of the trigger does not change with the state of the clock synchronization,
02
Q: what is a "line and" logic, in order to achieve it, what is the specific requirements on hardware features?
Two parallel in order to realize the output of the gate and logical functions become line and, on the hardware, the OC gate to implementation, at the same time on the output port and a pull resistance, because no OC gate may make irrigation current is too large, and burn out logic gate,
03
Q: explain the setup and hold time violation, drawing, and explains the solution?
Test chips Setup/hold time is the time between input signal and the clock signal, Setup time refers to the clock signal trigger rising along the arrival, the data of stable time,
Input signal should be clock rising edge ahead such as rising along the effective T time the chip, the T is to set up time - the Setup time, if you don't satisfy the Setup time, the data can't be a clock into the trigger, only the next clock up along the data to be into the trigger,
Hold time refers to the clock signal rise along the trigger after arrival, the data of stable time, if the hold time is not enough, the data can't be into the trigger,
Set up Time, Setup Time and Hold Time (Hold Time), set up Time refers to before the clock edges, data signal needs remain the same Time,
Keep time refers to the clock jump after edge data signals need to remain the same time,
If the duration of the data before and after the signal along the trigger in the clock than to build and maintain time, then more than the amount respectively referred to as the build time allowance allowance and keep time,
04
Q: what is the competition and adventure phenomena? How to judge? How to eliminate?
In combinational logic, the door of the input signal pathway after different time delay, the result in time to arrive at the gate of inconsistent called competition,
Produce burr called adventure, judgment method: algebraic method, graphic method (tangent cano, circle), table method (truth table), if the Boolean type may have the opposite signal occurring in the competition and adventure phenomena,
Risk is divided into partial "1" adventure and partial "0", the solution: one is to add a Boolean type of elimination; The second is on the outside of the chip capacitor; 3 it is to join the gating signal,
05
Q: explain the SRAM, SSRAM, SDRAM three noun?
SRAM: Static Random Access Memory (Static Random Access Memory, an SRAM) is a kind of Random Access Memory,
SSRAM: Synchronous Static Random Access Memory, namely Synchronous Static Random Access Memory,
SDRAM: synchronous dynamic random access memory (synchronous dynamic random access memory, SDRAM) interface is a synchronous dynamic random access memory (DRAM),
SSRAM all access to the clock up/down along the start, address and data input and other control signals are related to the clock signal, it is different from asynchronous SRAM, asynchronous SRAM access is independent of the clock, data input and output are controlled by the change of address, SDRAM, Synchronous DRAM Synchronous dynamic random access memory,
06
Q: the concept of FPGA and ASIC, what is the difference between them?
The FPGA programmable ASIC,
ASIC, application-specific integrated circuit, it is the circuit for special use, designed and made specifically for a user, according to a user's specific requirements, to lower development costs, short lead time to supply full custom, half a custom integrated circuits,
And gate array and other ASIC (Application Specific IC), compared them with the design development cycle is short, the design and manufacture of low cost, advanced development tools, without any test standard products, stable quality and the advantages of real-time online inspection,
07
Q: after the single chip microcomputer to electricity didn't work, the first thing to check?
(1) first of all should confirm whether the power supply voltage is normal, measured with voltmeter ground heel power supply voltage between the pins, whether the power supply voltage, the commonly used 5 v, for example,
(2) the following are a normal, check whether the voltage reset pin is measured by pressing the reset button and let go of the reset button on the voltage value, to see whether it is right,
(3) and then check whether the crystals is a lift, generally see with oscilloscope waveform of crystals pin; After checking above points, generally can be ruled out of order,
If the system is not stable, sometimes caused by bad power filtering, in the power of the microcontroller between heel to pin connected to a 0.1 uF capacitance will improve, if the power supply do not filter capacitance, then we'll need to pick up a larger filter capacitance, for example, the 220 uF, meet the system is unstable, can try and capacitance on chips (the closer, the better),
08
Q: what is synchronization logic and asynchronous logic?
Synchronization logic is a fixed causal relationship between the clock, asynchronous logic is no fixed causal relationship between all the clocks,
09
Q: do you know what are the common logic level? TTL and COMS level can be directly interconnected?
Commonly used logic level: 12 V, 5 V, 3.3 V,
TTL and CMOS can not direct interconnection, because the TTL is between 0.3 3.6 V, and the CMOS is have in 12 V at 5 V, CMOS output from TTL can be directly interconnected, TTL received CMOS need to pull up resistors in the output port plus one received 5 V or 12 V,
10
Q: how to solve the metastable?
Metastable refers to trigger can within a prescribed period of time was an identifiable state, when a trigger in metastable, can neither predict the output level of the unit, also can't predict when can output stability in a right level,
During the period of metastable, trigger output some intermediate grade level, or may be in a state of oscillation, and the useless output level can be along the signal channel of each trigger cascading down,
Solutions are:
Reduce the system clock;
Use a trigger (FF) react faster, LATCH (LATCH);
Introducing the synchronization mechanism, prevent the spread of metastable;
Improve the quality of the clock, rapid change in edge of the clock signal;
Use good craft, clock cycle allowance large devices,
11.
Q: latch, flip-flop, register is the difference between the three?
Trigger: capable of storing a binary signal are collectively referred to as the basic unit of circuit "trigger",
Latch: a trigger can only transmit or store a data, but in practice often want more than a transfer or storage data, therefore can connect multiple triggers the clock input of CP, with a control signal to control the public, and receive data independently various data port is still around, so that can more than one transmission or storage of data of the circuit is called a "latch",
Register: in the real number system, usually put can be used to store a set of binary synchronous sequential logic circuit is called registers, due to trigger with memory function, so the use of triggers can be easily constitute a register, as a trigger to store a binary code, so connect n trigger clock port can form a store n a binary code register,
Difference: from the perspective of register data, register and the latch function is the same, the difference is that register is synchronous clock control, and latch is potential signal control,
Visible, register and latches instruments have different applications, depending on the control mode and time relationship between data and control signals: if data signals effectively must lag behind control effectively, can only use the latch; If the data signals to control in advance and requires synchronization signals arrive, usable registers to store data,
12
Q: the difference between the synchronous reset and asynchronous reset in the design of IC?
Asynchronous reset is not affected by the clock, in a single chip system initialization (or electricity) need to be such a global signals to reset of the whole, the whole chip to a determination of the initial state, and the synchronous reset need in the clock strikes will be reset to the whole system,
13
Q: in the time domain design, how to deal with signals across time?
Signal communication between different clock domains synchronous processing is required, this will prevent the trigger is the first step on the new clock domain of metastable signals affect logic at a lower level, which can be used for a single control signal two-stage synchronizer, such as level, edge detection and pulse, the several signal can use FIFO, dual port RAM, hand signals, etc.,
Across the time domain signal passes through synchronizer synchronization, and prevent the spread of metastable, for example: 1 a signal of the clock domain, to send to the clock domain 2, so before the signal to the clock domain 2, should first after 2 synchronizer synchronization clock domain, can enter the clock domain 2,
The synchronizer is two levels of d flip-flop, the clock of the clock domain 2 clock, it is afraid of the clock domain 1 of this signal, and may not satisfy the clock domain 2 triggers the establishment of the holding time, and produce metastable, because there is no inevitable relations between them, is asynchronous,
It can prevent the spread of metastable but does not guarantee the correctness of the data mining came in, so usually only rarely digit signal synchronization, such as control signal, or address, when the synchronization is address, the address should be used commonly gray code, because gray code change each time a, equivalent to only one synchronizer at work, at a time so that we can reduce the error probability, as the design of asynchronous FIFO, more to read and write the address, is in this way,
If two clock domain between transmit a large amount of data, can solve the problem with asynchronous FIFO,
We can across ClockDomain when combined with a low level can make LockupLatch can to ensure that the Timing is correct,
14
Q: give the reg setup, hold time, for the delay of intermediate combinational logic?
Test chips Setup/hold time is the time between input signal and the clock signal, Setup time refers to the clock signal trigger rising along the arrival, the data of stable time,
Input signal should be clock rising edge ahead such as rising along the effective T time the chip, the T is to set up time - the Setup time. If you don't satisfy the Setup time, the data can't be a clock into the trigger, only the next clock up along the data to be into the trigger,
Hold time refers to the clock signal rise along the trigger after arrival, the data of stable time, when the hold time is not enough, the data can't be into the trigger, namely delay
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